The demand for computer system performance continues to grow to enable solutions to previously infeasible computing problems. In the past, computer architects met this performance demand by designing ever more complex microprocessor cores to exploit the abundance of transistors made available through advances in semiconductor fabrication.
Unfortunately, there are fundamental sources of bottleneck in sight that may impede the way to design and performance-scalability of future computer systems. In this talk, I will first briefly go over example projects addressing these bottlenecks which range from the lack of parallel software for future commodity multiprocessor chips, to reduced hardware and software robustness, to the memory system performance wall, and to the computer system design evaluation bottleneck.
I will then present in detail two technologies, one for error detection in computation in the presence of frequent hard/soft errors in future unreliable CMOS processes, and the other to simplify programming of future commodity multiprocessor chips.
Babak Falsafi is a Professor in the Department of Electrical and Computer Engineering at Carnegie Mellon, and a Visiting Professor of the School of Computer and Communication Sciences at EPFL. He co-directs the Computer Architecture Lab at Carnegie Mellon (www.ece.cmu.edu/CALCM), and is the Microarchitecture thrust leader for the MARCO Center for Circuit and System Solutions (www.c2s2.org).
His research targets architectural support for parallel programming, resilient systems, architectures to break the memory wall, and analytic and simulation tools for computer system performance evaluation. He is a recipient of an NSF CAREER award in 2000, IBM Faculty Partnership Awards in 2001, 2003 and 2004, and an Alfred P. Sloan Research Fellowship in 2004.
You may contact him at babak@cmu.edu (www.ece.cmu.edu/~babak).
He is a member of IEEE and ACM.
