The demand for computer system performance continues to grow to enable solutions to previously infeasible computing problems. In the past, computer architects met this performance demand by designing ever more complex microprocessor cores to exploit the abundance of transistors made available through advances in semiconductor fabrication.

Unfortunately, there are fundamental sources of bottleneck in sight that may impede the way to design and performance-scalability of future computer systems. In this talk, I will first briefly go over example projects addressing these bottlenecks which range from the lack of parallel software for future commodity multiprocessor chips, to reduced hardware and software robustness, to the memory system performance wall, and to the computer system design evaluation bottleneck.

I will then present in detail two technologies, one for error detection in computation in the presence of frequent hard/soft errors in future unreliable CMOS processes, and the other to simplify programming of future commodity multiprocessor chips.