Asynchronous Circuit and System Design Group

Asynchronous Open-Source DLX Processor (ASPIDA)

Asynchronous DLX Demo at ASYNC 2004 Conference

A demonstrator of asynchronous design and methodologies will be shown at several conferences this year, as part of the dissemination program of the ASPIDA IST project. The first occasion will be the ASYNC 2004 Conference, which this year is taking place in Hersonissos, Crete, Greece. Its goal is to illustrate the potentials of asynchronicity in the context of embedded systems, as well as the feasibility of a design flow for asynchronous circuits, based on standard tools and languages.

The demonstrator design was developed by the Asynchronous Circuits and Systems  Group of ICS-FORTH and of the University of Crete, and by the Microelectronics Group of Politecnico di Torino.

It consists of a simple embedded system, implemented on a Digilent D2E FPGA board, centered around ASPIDA DLX Processor, an asynchronous open-source version of the DLX RISC CPU.

Processor, memory and a VGA driver are implemented on a Xilinx Spartan IIE device using the ISE tools from Xilinx.
The whole system, including the asynchronous CPU and its interfaces to memories and legacy synchronous components, such as the VGA driver, was implemented on a standard FPGA device using standard design tools.

The ASPIDA open-source asynchronous DLX CPU supports the full instruction set of Hennessy and Patterson's DLX architecture (similar to the MIPS and other RISC processors). It is a fully-synthesisable and technology-portable Verilog design, which later in 2004 will also be fabricated as an ASIC, using Synopsys and Cadence tools. Its asynchronous implementation is based on the De-synchronization methodology. A cross-compilation design flow based on the GNU C compiler is also available.

To learn more about the DLX architecture and the ASPIDA DLX implementation click here...

To learn more about the clock-less De-synchronization methodology click here...

To learn more about the Xilinx flow and how it was used to implement the asynchronous DLX click here...

To learn more about the Demo System Implementation click here...

To see photos of the Demo board, the experimental setup and a Video of the Game of Life running on the DLX click here...


This work is sponsored by the EU (IST-2003-37796) ASPIDA project and by Xilinx Inc.



About CARV | People | Packet Switch Architecture | Advanced Computing Systems | Asynchronous Circuits and Systems | Scalable Systems and Networks | News | Publications | Contact Info
Site Map | Search | Help | Greek | English
Last revision date: 04 Oct, 2005 by

Last Content revision date: 04 Oct, 2005 by Asynchronous Circuits and Systems Group.