Asynchronous Circuit and System Design Group

Asynchronous Open-Source DLX Processor (ASPIDA)

Demo System Implementation

In the image above you can see a basic block diagram of the Demo System. Clicking on it will show a larger view of the block diagram.

The Demo System consists of the ASPIDA DLX, a memory interface that controlls the access to the CPU memory and the VRAM, and a VGA driver that controlls the video display.

To learn more about the memory interface and the memories click here...

To learn more about the VGA driver click here...



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Last revision date: 04 Oct, 2005 by

Last Content revision date: 04 Oct, 2005 by Asynchronous Circuits and Systems Group.