Asynchronous Circuit and System Design Group

Asynchronous Open-Source DLX Processor (ASPIDA)

ASPIDA DLX Processor
DLX Datapath Structure

The DLX is a 32-bit 5-stage pipelined RISC CPU architecture, first described in Hennessy and Patterson's book Computer Architecture: A Quantitative Approach. It is widely known, and its pipelined architecture resembles that of other leading embedded RISC processors, such as MIPS and ARM.
The EU-funded ASPIDA (ASynchronous oPen-source Ip of the Dlx Architecture) project has the goal of promoting the adoption of  asynchronous design, by delivering an open-source asynchronous synthesizable DLX processor core, supporting the full integer Instruction Set Architecture, interrupts and byte addressable memory. It will also deliver an asynchronous interconnect fabric based on the CHAIN architecture, developed by the University of Manchester.

To learn more about the DLX Architecture click here...

To learn more about the ASPIDA Open-Source DLX Processor features click here...
To learn more about the ASPIDA Asynchronous DLX ASIC and FPGA Implementations click here...
To learn more about the ASPIDA project, its aims and participants click here....




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Last revision date: 04 Oct, 2005 by

Last Content revision date: 04 Oct, 2005 by Asynchronous Circuits and Systems Group.