Asynchronous Circuit and System Design Group

Asynchronous Open-Source DLX Processor (ASPIDA)

Xilinx FPGA flow used for asynchronous
Despite using the standard Xilinx FPGA tools, it was necessary to lead the tools in a more elaborate manner for the implementation of the de-synchronized DLX, in order to achieve the desired outcome. Leading the tools was achieved in two ways, specifying specific constraints to instances of the design, e.g. delay elements, low-skew lines, etc. and floorplanning.

The use of timing, don't touch, low-skew and placement constraints is crucial for the implementation of de-synchronized circuits using an FPGA EDA flow. These principles of course apply to the ASIC flow as well. Luckily, we were always able to find appropriate constraints supported by the ISE tools, however some of these were not supported appropriately by the SPARTAN 2E device. The most significant problem posed by the use of this device was the presence of only two low-skew networks on it, and the lack of flexibility for tapping signals to local clock spines.

The de-synchronized design has been produced from the synchronous design by removing the clock and replacing it with asynchronous controllers. The datapath has not been changed. The new design has to be synthesized by the Xilinx synthesizing tool. The synthesis of the datapath can be performed as in the case of the datapath of a synchronous circuit. The usual optimizations for speed can be applied. The synthesizer should try to eliminate setup/hold violations as it would do for a synchronous circuit. Timing driven synthesis is desirable.

In the case of the asynchronous control circuit, however, the situation is different. The synthesis tool has to be provided with special constraints that will guide the synthesis process. The logic of the asynchronous parts of the design is typically intolerable of optimizations. Timing optimizations may change the behavior of the circuit thus making it non-operational. Area optimizations can equally alter the functions that the circuit is supposed to perform. It is important that the synthesis tool produces exactly the circuit that the designer has constructed.

The mapper needs to be supplied with guiding information for the mapping of the asynchronous parts. The tool has to be instructed not to remove logic that seems redundant or feedback paths. The mapping of the datapath can proceed as usual and the napper is free to apply the best algorithms for optimizing the design for area or performance.

The placement of the datapath is similar to the placement procedure of any synchronous circuit. Asynchronous control circuits designed according to the Delay-Insensitive or Quasi Delay-Insensitive models can be placed in any way with no impact on circuit correctness. The de-synchronization controllers are Quasi-delay insensitive circuits. Matched-delay elements however are very sensitive to placement, as if spread out on a large area, routing delays can render their delay much larger than originally intended. After the routing is completed, Static Timing Analysis (STA) is necessary to determine whether the delay of the datapath matches its corresponding matched delay element.

For more information on the synthesis procedure click here...

For more information on the mapping and the place and route procedure click here...



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Last revision date: 04 Oct, 2005 by

Last Content revision date: 04 Oct, 2005 by Asynchronous Circuits and Systems Group.