Over the last decades, design sizes have increased to million fold since Moore?s law was introduced in 1965. The increasing size and complexity of today?s designs introduces many  challenges to the design and verification goals, tasks, processes, and risks. All previously mentioned challenges, and more, result in a noticeable increase in the effort spent on  verification, and have forced the industry to adopt various new functional verification techniques. Nowadays more than 60% of the life of a project is spent on Verification due to the increased complexity of the design.

This talk is about Design and Verification methodologies and strategies such as the Universal Verification Methodology (UVM), formal, assertion-based and power-aware techniques, that  shorten the time to market  and minimize the risk that expensive post-silicon errors bring for high quality (complex) products.