This talk describes the first (and so far only) integrated 10 gigabits ethernet tranceiver dissipating under 1-Watt of power while exceeding all the relevant performance specifications. The talk begins by briefly introducing the IEEE-802.3ae physical layer standard and outlining some of the challenges in achieving high density switching at 10Gbps line rate. Novel techniques that minimize the physical layer power/performance ratio are then described: single source plesiochronous clocking, 5-GHz CMOS logic and resonant 10-GHz clock distribution followed by characterization results.
( Work presented in the International Solid State Circuits Conference 2004).