Embedded and Scalable Multiprocessor System Architecture, Interprocessor Communication Mechanisms, Interconnection Network Architecture, Packet Switch Architecture, Computer Architecture, VLSI Systems.
Award by the Secretary General of the Region of Crete 2003 - jointly with Stelios Orphanoudakis and Panos Constantopoulos - as the Principal Organizers of the Department of Computer Science, University of Crete.
Manolis Katevenis received his Ph.D. degree in Computer Science from the University of California, Berkeley, in 1983. From January 1984 to March 1985 he was Assistant Professor of Computer Science at Stanford University, Stanford, California, USA. Since September 1985, he is with the University of Crete, Dept. of Computer Science, where he is currently a Professor; according to an Award by the Secretary General of the Region of Crete in 2003, Katevenis is recognized as one of the three Principal Organizers of this Department. Since 1985, he is also with the Institute of Computer Science (ICS), FORTH, Heraklion, Crete, where he is currently Deputy Director, and the Head of the Computer Architecture and VLSI Systems Laboratory. In 2003-2004, he was a founding partner of HiPEAC, the European Network of Excellence on High-Performance and Embedded Architecture and Compilation, where he is now a member of the Steering Committee and coordinator of Interconnection Networks Architecture.
His interests are in: Scalable Multicore Systems - Interprocessor Communication and Memory Architecture; Interconnection Network Architecture; Packet Switch Architecture; Computer Architecture; and VLSI Systems.
During his doctoral studies (1980-83), he was the chief implementor of the RISC II single-chip microprocessor at U.C.Berkeley (precursor of the SUN SPARC architecture), and for this thesis he received the 1983 Sakrison Memorial Prize and the 1984 ACM Doctoral Dissertation Award. The RISC ideas revolutionized the microprocessor industry in the late 80's. After Berkeley, he consulted for AMD during the design of the "AMD-29000" RISC microprocessor, for Daisy Systems during the design of a hardware accelerator, for two other companies during the design of very-high speed RISC processors in ECL and GaAs, for a Storage Area Networking (SAN) company, and for DEC, SRC, where he did the preliminary switch design for "Autonet", precursor of DEC's "ATM GigaSwitch". In 1987, during the first meetings of the IEEE Standard 1596-1992 Scalable Coherent Interface (SCI) Committee, he was the first to propose using point-to-point connections rather than a bus architecture.
In 1985-91, he made pioneering contributions in per-flow queueing, backpressure, congestion tolerance, and weighted round-robin scheduling, yielding weighted max-min fairness in switches for high speed networks --topics whose industrial application is seen one or two decades later. In 1991-92, he worked on switch design for multiprocessor interconnection networks. In 1996-98, Katevenis was the technical leader of the design of ATLAS I, a 6-million-transistor single-chip 16x16 ATM switch, implemented in 0.35-micron CMOS, featuring 10 Gb/s throughput, sub-microsecond cut-through latency, and credit-based flow control (backpressure) at the granularity of 32 thousand virtual channels. In 1998-2001, he introduced wormhole IP over ATM, and led the design of pipelined heap management for schedulers in multi-gigabit weighted fair queueing, and hardware for managing thousands of queues in DRAM at 10 Gb/s line rate. In 2002-2005, his research concerned the architecture of and congestion management in non-blocking switching fabrics with internal backpressure, and distributed scheduling in buffered crossbars. In 2006-2011, he worked on networks-on-chip (NoC), including the micro-architecture of high-radix on-chip crossbar switches.
Katevenis' work on parallel processing started in 1993-95, when he led the Telegraphos project in ICS-FORTH, where workstation clustering prototypes were designed and built, based on remote-write, remote-DMA, and remote-enqueue operations, including processor-network interfaces for protected user-level communication. Since 2006, his research concerns interprocessor communication and memory architecture in on-chip and system-wide embedded and scalable multi-processor systems. In the SARC project, he led the design of an architecture and FPGA protoype that unifies explicit and implicit communication by integrating the network interface with the cache controller, basing their common operation on a configurable event-response harware mechanism.