Networks-on-chip connect the processing elements (PEs) in the chip, forwarding traffic with the lowest possible latency and with a limited power and area budget. Their design faces multiple difficulties, including the complexity of the router, a significant power consumption, limited frequency and bisection bandwidth, potential deadlocks, and reduced bandwidth (i.e. not exploiting all the available wiring resources on chip). In this talk, I will overview these limitations and present a selection of recent proposals that attack them, a few of them from my group.

Routerless Multi-Ring NOCs are recent proposals to interconnect the PEs that solve many of the limitations of traditional NOCs. Instead of mesh-connected routers, they employ a plurality of (almost) independent register-insertion rings, laid out such that any two PEs share at least one ring. Source routing merely selects an appropriate ring that reaches the destination. This approach presents many advantages, such as reduced power and area, high frequency and exploiting available wiring resources. However, in the talk I will present some identified limitations of them. In particular, it will focus on the selection of the set of rings (akin to the topology) and potential deadlock and congestion issues, together with some proposals for the research stay.