Integrated circuit design has seamlessly entered the power-limited scaling regime, where the traditional goal of achieving the highest performance has been displaced by optimization for both performance and power.

Multi-GHz microprocessors are an example of power-constrained designs where efficient circuit topologies and techniques are required to achieve high operating frequencies while keeping power consumption to a resonable level. Therefore, the design of energy-delay efficient datapaths which are employed for the execution of the processor's integer and floating point instructions as well as the execution of media-oriented SIMD instructions is of high importance. In this talk, at first we will briefly present an optimization framework that allows the designer to explore the whole energy-delay space of each design and to quantify the benefits earned from new circuit techniques and logic-level optimizations. In the following, we will present a variety of new datapath circuits and design techniques that are based on an inherently simpler implementation and offer superior performance in the energy-delay sense.