NanoStreams co-designs a micro-server architecture and software stack that address the unique challenges of hybrid transactional-analytical workloads, which are encountered by emerging applications of real-time big-data analytics. To this end, NanoStreams brings together embedded system design principles, application-specific compilers, and HPC software practices.

The processor technology that underpins the NanoStreams micro-server is an amalgam of RISC cores and nano-cores, a new class of programmable custom accelerators. Novel automatic compiler generation and parameterization technology enables low-effort programming and integration of nano-cores into application-specific, many-core accelerators. The proposed heterogeneous Analytics-on-Chip processor forms the backbone of the NanoStreams micro-server, which further leverages a hybrid DRAM-PCRAM memory system and a non-cache-coherent scale-out architecture to achieve extreme energy-efficiency. The software stack of the NanoStreams micro-server is rooted in domain-specific languages for analytical queries, which the project implements with a streaming dataflow execution model. The language runtime system uses real-time scheduling, performance isolation techniques and region-based memory management to minimize latency on the transactional path and maximize throughput on the analytical path. NanoStreams virtualizes lightweight PCRAM-based persistent memory, for direct user access and locality optimization.

The project will deliver a real-silicon prototype, based on the Xilinx Zynq platform and ARM-Linux. The quantitative objective of NanoStreams, in comparison with contemporary HPC servers, is to reduce analytical response time of commercial in-memory databases by at least 30%, while sustaining transactional throughput and improving system energy-efficiency and programmability. NanoStreams will demonstrate these advances with industry-standard workloads and four real-world case studies.