module lc_semi_dec(rst, ri, ai, ro, ao, l, delay_select);

input rst, ri, ao;
input [1:0] delay_select;
output l, ai, ro;

wire ridp, ridm; // pulse and matched delayed ri //
wire nl;
wire nrst, lninp1, lninp2;
wire roainp;
wire ridp1,ridp2,ridp3;

//synthesis attribute keep of ridp2 is true
not not3(ridp2,ridp1);
//synthesis attribute keep of ridp3 is true
not not4(ridp3,ridp2);

//##synthesis attribute keep_hierarchy of pd is yes
 pulse_delayIF pd(.inp(ri), .outp(ridp), .outp1(ridp1));
//##synthesis attribute keep_hierarchy of md is yes
 matched_delayIF md (.inp2(ridp), .inp3(ridp3), .outp2(ridm), .delay_select(delay_select));
 wire ro_master,ao_master,l_slave;
 master_ctrl master_ctrl_(rst, ridm, ai, ro_master, ao_master, l);

 slave_ctrl  slave_ctrl_(rst, ro_master, ao_master, ro, ao, l_slave);

 // #synthesis attribute CLOCK_SIGNAL of l is YES
 // #synthesis attribute CLOCK_SIGNAL of ai is YES
 // synthesis attribute TIG of ri
 // synthesis attribute TIG of ao
 // #synthesis attribute MAX_FANOUT of lc_semi_decIF is 30