ATLAS I a Single-Chip ATM Switch with Credit-Based Flow Control
                                                             [1997-12]

ATLAS I is a single-chip gigabit ATM switch, under development by the
ASICCOM Consortium, in the framework of the European Union ACTS Programme.
ATLAS I is designed in the Institute of Computer Science (ICS),
Foundation for Research & Technology - Hellas (FORTH), in the
Science and Technology Park of Crete (STEP-C), Heraklion, Crete, Greece.
The ASICCOM Consortium consists of industrial partners (INTRACOM,
Greece; SGS THOMSON, France and Italy; BULL, France), telecom operators
(TELENOR, Norway; TELEFONICA, Spain), and research institutes (FORTH,
Greece; SINTEF, Norway; Polit. di Milano, Italy; Democritos, Greece).

ATLAS I is a general-purpose building block for high-speed communication
in wide (WAN), local (LAN), and system (SAN) area networking, supporting
a mixture of services from real-time, guaranteed quality-of-service to
best-effort, bursty and flooding traffic, in a range of applications
from telecom to multimedia and multiprocessor NOW.  This four million
transistor 0.35-micron CMOS chip features [1] [2]

Advanced Architecture

 10 Gigabits outgoing throughput, with GBaud serial links and
  with link bundling
  16x16 configuration, at 622 Mbpslink (per direction), or
  8x8 configuration, at 1.24 Gbpslink, or
  4x4 configuration, at 2.5  Gbpslink, or
  2x2 configuration, at 5.0  Gbpslink, or combinations of the above
  (e.g. 12 ports at 622 Mbps and 1 port at 2.5 Gbps, etc.)

 sub-microsecond cut-through latency

 multicasting (in hardware)

 three priority levels (service classes), 54 (logical) output queues [3]

 on-chip shared buffer (256 ATM cells)

 on-chip VPVC translation table (4096 entries)

 load monitoring hardware support for the accelerated measurement
  of the cell loss probability (CLP) of the real traffic going
  through the switch.  The accelerated measurement algorithm allows
  real-time monitoring and decision making, even in cases where the
  CLP is so low that normal measurement methods would be inappropriate
  for real-time operation due to the required long measurement time.

 credit-based flow control

The chip can be optionally configured to implement credit-based flow
control (multi-lane back-pressure), in hardware, at the individual
cell level, at the granularity of 4096 flow groups per link [3].
Network systems can take advantage of this feature in any or all
of the following ways

 A large switch box can be built, with hundreds or thousands of
ports, using a switching fabric made of ATLAS I chips, where
multi-lane back-pressure is used inside the box to provide the high
performance of output queueing at the low cost of input queueing [3].
Any desired flow control method can be employeed outside the box.

 Networks that employee credit-based flow control can be built
directly out of ATLAS I chips.  In system area (SAN) or local
area (LAN) environments, the low latency and the multi-lane
back-pressure of ATLAS I provide ATM networking with the features
and performance of wormhole routing; this is an ideal setting for
making networks of workstations (NOW) that provide multi-processor
performance at affordable cost.  The multi-lane architecture and
the multiple priority levels of ATLAS I offer superior behavior.

 In wide area networking (WAN), although the ATM Forum has opted
for rate rather than credit based flow control, the Quantum Flow
Control (QFC) Consortium still insists that credit-based flow control
performs much better;  recent experimental results by research
groups have started pointing to the same conclusion.  ATLAS I
offers a company the advantage of being ready to deploy credit
flow controlled networks, if the market goes in that direction.

Detailed information about ATLAS I can be found in

[1]  httparchvlsi.ics.forth.gratlasI

[2] ATLAS I  A General-Purpose, Single-Chip ATM Switch with
 Credit-Based Flow Control (by Katevenis, Serpanos, Vatsolaki),
 Hot Interconnects IV Symposium, Stanford Univ., CA, USA, Aug. 1996; URL
 ftpftp.ics.forth.grtech-reports19961996.HOTI.ATLAS_I_ATMswitchChip.ps.gz

[3] Switching Fabrics with Internal Backpressure using the ATLAS I
 Single-Chip ATM Switch (by Katevenis, Serpanos, Spyridakis),
 GLOBECOM'97 Conf. Proc., Phoenix, AZ USA, Nov. 1997, pp. 242-246; URL
 ftpftp.ics.forth.grtech-reports19971997.GLOBECOM.ATLAS_I_Fabrics.ps.gz

For further information, please contact
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Manolis Katevenis,   Professor of Computer Science,  Univ. of Crete
Head,  Computer Architecture and VLSI Systems Division,   Institute
of Computer Science, Foundation for Research & Technology -- Hellas

E-Mail  katevenis@ics.forth.gr   Tel +30 (81) 391664  Fax 391661

Air-Mail     ICS,  FORTH,  Science and Technology  Park  of Crete,
Vassilika Vouton, P.O. Box 1385, Heraklion, Crete, GR 711 10 Greece
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