Date: 09 March 2016 Time: 16:30 - 18:00
Location: "Alkiviades C. Payatakes" Seminar Room, FORTH, Heraklion, Crete
Host: Prof. Manolis Katevenis
Over the last decades, design sizes have increased to million fold since Moore?s law was introduced in 1965. The increasing size and complexity of today?s designs introduces many challenges to the design and verification goals, tasks, processes, and risks. All previously mentioned challenges, and more, result in a noticeable increase in the effort spent on verification, and have forced the industry to adopt various new functional verification techniques. Nowadays more than 60% of the life of a project is spent on Verification due to the increased complexity of the design.
This talk is about Design and Verification methodologies and strategies such as the Universal Verification Methodology (UVM), formal, assertion-based and power-aware techniques, that shorten the time to market and minimize the risk that expensive post-silicon errors bring for high quality (complex) products.
Giorgos Nikiforos graduated from the Computer Engineering & Informatics Department of the University of Patras in 2006. In 2009, he received the Master's degree from the Computer Science Department of the University of Crete. Then, until 2011, he worked as a Hardware Engineer in the Computer Architecture and VLSI Systems Laboratory of FORTH-ICS. From 2011 until 2014, Giorgos Nikiforos worked at Intel, Barcelona, as an IC Design Verification Engineer for the 2nd generation of Intel Xeon Phy. Since 2014, Giorgos is with Broadcom Barcelona, where he is Senior IC Design Verification Engineer for a custom ARMv8 core; recently, he got promoted to Principal IC Design Verification Engineer.