Lecture

An 800mW 10 Gigabit Ethernet Transceiver in 0.13-um CMOS
29.09.2005
Speaker: Dr. STEFANOS SIDIROPOULOS, Chief Technical and Chief Executive Officer, Aeluros Inc.
Date: 29 September 2005 Time: 11:10-12:00
Location: Mediterranean Studies Seminar Room - FORTH
Host: Manolis Katevenis

Abstract:

This talk describes the first (and so far only) integrated 10 gigabits ethernet tranceiver dissipating under 1-Watt of power while exceeding all the relevant performance specifications. The talk begins by briefly introducing the IEEE-802.3ae physical layer standard and outlining some of the challenges in achieving high density switching at 10Gbps line rate. Novel techniques that minimize the physical layer power/performance ratio are then described: single source plesiochronous clocking, 5-GHz CMOS logic and resonant 10-GHz clock distribution followed by characterization results.

( Work presented in the International Solid State Circuits Conference 2004).

Bio:

Stefanos Sidiropoulos received his BS and MS in Computer Science from the University of Crete and his PhD in Electrical Engineering from Stanford University in 1997. He has worked in both development and research groups at DEC/WRL, IIT, MIPS and Rambus. Since 2001 he is with Aeluros Inc., a startup company focused on ICs for optical communications. He has been a co-founder of the company, and he is currently the Chief Executive and the Chief Technical Officer. He has been a program committe member of the Intenational Solid State Circuits Conference and a visiting lecturer at Stanford University. His work interests are in mixed signal circuit design, VLSI microarchitectures, CAD and design methodology.

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