Design and Implementation of a 1.2 Gbit/s ATM Cell Buffer using a Synchronous DRAM Chipby George N. Glykopoulos
Technical Report FORTH-ICS/TR-221
Master of Science Thesis, Department of Computer Science, University of Crete
The purpose of this work was to demonstrate this capability in a working prototype, gaining familiarity with the practical details of SDRAM and SONET operation, and PCB implementation with 100MHz clocks. The prototype that was designed, manufactured and successfully tested, is an 8-layer PCB with two SONET OC-3 links (2 x 155.52Mbit/s incoming and 2 x 155.52Mbit/s outgoing throughput), interfaced to an SDRAM chip using two ALTERA FPGA's. The board also includes a microprocessor interface and PLL-driven clock generators/drivers.
The Full Technical Report is Available in:
- gzip'ed Postscript (1 MByte, 70 pages, in English)
© Copyright 1998 by FORTH.
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Last updated: January 1999, by M. Katevenis.