Low-Latency Networks-on-Chip (NoC)Giorgos Passas, George Michelogiannakis, Dionisios Pnevmatikatos, Manolis Katevenis
- Preprint in PDF (200 KBytes) - © Copyright 2011 by ACM.
- Presentation Slides in PDF (360 KBytes) - © Copyright 2011 by FORTH.
- Preprint in PDF (70 KBytes) - © Copyright 2010 by ACM/IEEE.
- Presentation Slides in PDF (210 KBytes) - © Copyright 2010 by FORTH.
- Preprint of March 2007 in PDF (130 KBytes) or PS (400 KBytes); 10 pages - © Copyright 2007 by IEEE.
- Presentation Slides in PDF (400 KBytes) - © Copyright 2007 by FORTH.
Other past work in Packet Switch Architecture:
- Buffered Crossbar (CICQ), Variable-Size Packet Switching.
- Benes Fabrics with Internal Backpressure for Scalable Non-Blocking Switching.
- Multi-Lane Architectures for Robust and Secure Communication Networks.
- Weighted-Round-Robin Scheduling:
- Per-Flow Queueing.
- Flow Control: ATLAS I: 10 Gb/s single-chip ATM switch with backpressure (1995-99).
- Wormhole IP over ATM.
- Pipelined Memory Shared Buffer for VLSI Switches.
- Packet Switch Architecture: another list, similar to this one, of past projects in this area in FORTH-ICS-CARV.
© Copyright 2007-2012 by FORTH or the IEEE:
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