ICS Publications - CARV

Technical & Research Reports (96)

          M.S. Theses

        1. Stavrakantonaki, E. (2016). A static pointer analysis on intermediate representation for compilation optimizations
        2. Vasilakis, E. (2015). An Instruction Level Energy Characterization of ARM Processors
        3. Papakonstantinou, N. (2015). Combining Recursively Parallel Runtimes with Blocked-based Dependence Analysis
        4. Papoulas, C. (2015). Design and Implementation of a Social Networking Architecture for Cloud Deployment Specialists
        5. Glenis, A. (2015). FT-Myrmics : A fault tolerant runtime system for task based programming models
        6. Papagiannis, A. (2013). Implementing Scalable Parallel Programming Models with Hybrid Address Spaces
        7. Stamatakis, D. (2012). Scalability of Replicated Metadata Services in Distributed File Systems
        8. Chasapis, K. (2012). Bladefs: Design and Implementation of a kernel level file system for scalable storage servers
        9. Papatriantafyllou, A. (2012). Efficient and Accurate Block-Level Dependence Analysis For Task Dataflow Models
        10. Zakkak, F. S. (2012). SCOOP: Language extensions and compiler optimizations for task-based programming models
        11. Klonatos, I. (2011).  Design and Evaluation of Solid-State Drive (SSD) Caches to Improve Storage I/O Performance. University of Crete.
        12. Tsaliagkos, D. (2011). Design and Implementation of a Directory based Cache Coherence Protocol
        13. Saloustros, G. (2011). Design and Implementation of a Scalable Storage System for Fully-Consistent Replicated Data Logging
        14. Kesapidis, I. (2011). Dynamic Dependence Analysis on Multi-core Processors
        15. Fountoulakis, M. (2010). DARC: Design and Evaluation of an I/O Controlller for data Protection. May 2010.
        16. Alvanos, M. (2010). Design and Evaluation of a Task -based Paraller H.264 Video Encoder for the Cell Processor. July 2010.
        17. Koukos, K. (2010). Locality management in task-based parallel programming models. August 2010.
        18. Zampetakis, M. (2010). Runtime support for programming explicit communication chip multiprocessors. July 2010.
        19. Sempepou, Z. (2010). Scalable storage support and fault-tolerance for data stream processing systems. July 2010.
        20. Katsamali, M. (2010). Software implementation of MPI primitives in multicore FPGA. June 2010.
        21. Makatos, A. (2010). ZBD: Using Transparent Compression at the Block Level to Increase Storage Space Efficiency. March 2010.
        22. Nikiforos, G. (2009). FPGA implementation of a cache controller with configurable scratchpad space. April 2009.
        23. Tzenakis, G. (2009). Tagged Procedure Calls (TPC): Efficient runtime support for task-based parallelism on the Cell Processor. November 2009.
        24. Kasapaki, E. (2008). An EDA Tool for the Timing Analysis, Optimization and Timing Validation of Asynchronous Circuits. 2008.
        25. Passas, S. (2008). Analysis and Optimization of Overheads in Communication Protocols Over High Speed Ethernet-based Cluster Interconnects. April 2008.
        26. Mangas, E. (2008). Fine-grained Localization in Wireless Sensor Networks using Acoustic Sound Transmissions and High Precision Clock Synchronization. December 2008.
        27. Aslanidis, I. (2008). Multi-valued logic synthesis. April 2008.
        28. Pantelias, E. (2008). Αποσυγχρονισμός Βιομηχανικών Κυκλωμάτων. April 2008.
        29. Michelogiannakis, G. (2007). Approaching Ideal NoC Latency with Pre-Configured Routes. September 2007.
        30. Matthaiakis, P. (2007). Gated Dual-Rail - A Methodology for Reducing the Power Consumption of Monotonic Dual-Rail Circuits. December 2007.
        31. Papamichail, M. (2007). Network Interface Architecture and Prototyping for Chip and Cluster Multiprocessors. September 2007.
        32. Andrikos, N. (2006). A Fully-Automated Desynchronization Flow for Synchronous Circuits. April 2006.
        33. Vlachos, E. (2006). Design and Implementation of a Coherent Memory Sub-System for Shared Memory Multiprocessors. April 2006.
        34. Kotsis, G. (2006). Improving Scalability on Shared Memory Clusters. December 2006.
        35. Passas, G. (2006). Packet Mode Scheduling in Buffered Crossbar Switches. April 2006.
        36. Panagiotakis, G. (2006). Reducing Disk I/O Performance Sensitivity for Large Numbers of Sequential Streams. September 2006.
        37. Giannakopoulos, I. (2005). CORMOS: A Communication-Oriented Runtime System for Wireless Sensor Networks. April 2005.
        38. Papaefstathiou, V. (2005). Design and Implementation of Network Packet Classification Engines. April 2005.
        39. Dokianaki, O. (2005). Evaluation of Asynchronous Interconnect Techniques for Digital SoC. April 2005.
        40. Xynidis, D. (2005). Performance Analysis and Scaling of Networked Shared Block-Level Storage. December 2005.
        41. Kounalakis, E. (2005). The Mythical IP Block: An Investigation of Contemporary IP Characteristics. December 2005.
        42. Simos, D.G. (2004). Design of a 32x32 Variable Packet-Size Buffered Crossbar Switch Chip. November 2004.
        43. Xynidis, K. (2004). Network Intrusion Prevention on Multilevel Processing Architectures. November 2004.
        44. Sarmpanis, A. (2004). Ένα Πρωτόκολλο Εκμισθώσεων για την Ενημέρωση Δεδομένων Προσωρινών Μνημών peer-to-peer δικτύων. November 2004.
        45. Charitakis, I. (2004). Εφαρμογές του Επεξεργαστή Δικτύων IXP 1200 σε Συστήματα Ανίχνευσης Εισβολέων για Δίκτυα. April 2004.
        46. Papachristos, Ch. (2002).  Navigation Technologies over low bandwidth links for Thin Clients An introduction to the CC/PP protocol. December 2002.
        47. Kapsalis, D. (2002). Design and Implementation of a per-Flow Queue Manager of an ATM Switch using FPGA Technology. March 2002.
        48. Charteros, K. (2002). Fast Parallel Comparison Circuis for Scheduling. March 2002.
        49. MeÃntanis, D. (2002). Hardware Conversion and Software Import to a Prototype Microprocessor Board. December 2002.
        50. Kalyvianaki, E. (2002). Î§-PacketQ a network tragic visualization tool. A reial-time approach for multiple users. December 2002.
        51. Lymperis, S. (2002). Implementation of a Motion Compensaation Subsystem for an MPEG-II Decoder. December 2002.
        52. Chrysos, N. (2002). Weighted Max-Min Fair Scheduling, for a Crossbar, with Small Internal Memory. 2002.
        53. Sapountzis, G. (2002). Πλέγματα Μεταγωγής BENES με Εσωτερικό Backpressure Πολυπλοκότητας O(N). December 2002.
        54. Papadakis, G. (2001). Design and FPGA Implementation of an ABR traffic scheduler and utopia interfaces for an ATM network switch. November 2001.
        55. Gialama, A. (2001). Distributed Video Server with Quality of Service. June 2001.
        56. Asimakopoulou, X.A. (2001). Effective Resource Discovery on the World Wide Web. June 2001.
        57. Danalis, A. (2001). Firewall development for the embedded network processor IXP1200. July 2001 .
        58. Lolas, Ch. (2001). Low Level Software Design and Implementation for High Performance Packet Switches. November 2001.
        59. Ioannou, A. (2000). An ASIC Core for Pipelining Heap Management to Support Scheduling in High Speed Networks. November 2000.
        60. Oikonomou, A. (2000). Architecture and Implementation of an Adaptation Bridge for ATM Networks. June 2000.
        61. Flouris, M.D. (2000). Design & Implementation of Methods Enchancing the Performance of www Proxies. March 2000.
        62. Nikologiannis, A. (2000). Efficient Per-Flow Queuing in DRAM at OC-192 Line Rate using Out-of-Order Execution Techniques. November 2000.
        63. Sidiropoulos, A. (1999). Distributed Indexing and Searching Mechanisms. March 1999.
        64. Chatzistamatiou, A. (1999). EasyAgent: a Masif Compliant Environment for Mobile Java Objects. March 1999.
        65. Papathanasiou, A E. (1999). Effective Resource Discovery on the World Wide Web. June 1999.
        66. Milolidakis, G. (1999). MemSpyer: A Performance Debugging Tool which simulates and visualizes memory hierarchy. March 1999.
        67. Glykopoulos, G. (1998). Design and Ιmplementation of an 1.2 Gbit/s ATM Cell Buffer using a Synchronous DRAM chip. July 1998.
        68. Karakonstantis, P. (1998). Efficient Memory Management for high-speed ATM networks. November 1998.
        69. Kornaros, G. (1997).  Implementation of Pipelined Multi- Queue Management in the ATLAS I Switch in Full- Custom CMOS VLSI. June 1997.
        70. Zarras, A. (1997). Array Tracer : Parallel Performance Analysis and Visualization. March 1997.
        71. Gkanas, L. (1997). New Caching ways in the World Wide Web. 1997.
        72. Terzis, S. (1997). Performance Monitoring in Digital Library Systems. November 1997.
        73. Artavanis, M. (1997). Simulation of the Shared Discks Architecture for Transaction Processing Systems. November 1997.
        74. Moraiti, M. (1997). Trace-driven Simulation of ATM and Wormhole networks. November 1997.
        75. Anastasiadi, A. (1996).  A study of Microeconomic Algorithms for Load Balancing and Data Replication in Distributed Computer Systems. November 1996.
        76. Spyridakis, E. (1996). Comparative Study of Credit Flow Controled ATM and Wormhole Networks Under Bursty Traffic and Witg Hot Spots. 1996.
        77. Papachristos, K. (1996). Design and Implementation of the Telegraphos Operations for the Mach Operating System. March 1996.
        78. Dramitinos, G. (1996). Reliable Paging to Remote Main Memory in a Workstation Cluster. 1996.
        79. Ioannidis, S. (1996). Using the Remote Main Memory in a Workstation Cluster for Reliability and Performance in Transactional Based Systems. November 1996.
        80. Sareidakis, T. (1995). Array Tracer: A Parallel Performance Analysis Tool. November 1995.
        81. Efthymiou, A. (1995). Design of a 25 Gbits/sec Pipelined Menory for Shared Buffer Network Switches. November 1995.
        82. Marazakis, M. (1995). Simulation and Transaction Processing Systems and A Study of Methods for Performance Goal Satisfaction. November 1995.
        83. Lamprinidis, A. (1995). Μέθοδοι Ταξινόμησης Δοσοληψιών σε Ομάδες με Παρόμοια Χαρακτηριστικά Φόρτου Εργασίας. November 1995.
        84. Karavasili, M. (1994). An Algorithm to Layout Directed Graphs. March 1994.
        85. Dimitriadis, G. (1994). An Arithmetic Entropy Codec VLSI chip for JPEG compression. March 1994.
        86. Xanthaki, Z. (1994). Ενας Ελεγκτής για Διαφύλλωση Προσπελάσεων σε ένα Απλό Rambus. March 1994.
        87. Farsaris, I. (1993). Design and Implementation of undo-redo mechanism in Labyrinth System. May 1993.
        88. Karydis, N. (1993). Βιβλιοθήκη Γεωμετρικών Κυττάρων και Μετασχηματισμών για τον Λαβύρινθο. April 1993.
        89. Moschovos, A. (1992). Implementing non-numerical algorithms on a decoupled architecture supporting software pipelining.  (pdf in english) (pdf in greek).
        90. Kalogerakis, P. (1992). Ο Μηχανισμός Υπολογισμού Κυττάρων στο Λαβύρινθο. September 1992.
        91. Sorilos, A. (1992). Οντοκεντρικός Σχεδιασμός Γραφικών στο Σύστημα Λαβύρινθος. September 1992.
        92. Vatsolaki, P. (1992). Σχεδίαση Ενός Υψηλής Ταχύτητας UART Δομικού Στοιχείου για Βιβλιοθήκες Ολοκληρωμένων Κυκλωμάτων VLSI. 1992.
        93. Georgis, Ch. (1992). Σχεδιασμός και Υλοποίηση του Γραφικού Τμήματος του Λαβυρίνθου. March 1992.
        94. Sidiropoulos, S. (1991). A General Purpose ATM Switch Chip: Architecture and Feasibility Study. September 1991.
        95. Tzartzanis, N. (1991). Αναδιάταξη Κώδικα σε Μνήμη Διπλού Πλάτους για Ελάττωση του Κόστους των Διακλαδώσεων. June 1991.
        96. Chalkiadakis, V. (1990). Αρχική Σχεδίαση και Υλοποίηση του Ring 64: Δίκτυο Τοπολογίας Δακτυλίου για Πακέτα Δεδομένων και Φωνής με Ταχύτητα Μεγαλύτερη από 64 Mb/s. December 1990.
              Found: 96 publications
              Conditions of Use | Privacy Policy