ICS Publications - CARV

Technical & Research Reports (107)

        ICS-FORTH Technical Reports

      1. Zakkak, F. S. (2017). Java on Scalable Memory Architectures. 2017.TR464_JAVA_on_Scalable_Memory_Architectures.pdf.
      2. Fatourou, P., Kallimanis, N., Kanellou, E.K., Makridakis, O., & Symeonidou, C. (2015). Distributed data structures for future many-core architectures. 2015.TR447.Apr2015.pdf.
      3. Poulios, P.D. (2015). Low-Latency Implementation of Network Sockets over Remote DMA. 2015.TR455_Low-Latency_Network_Sockets_Remote_DMA.pdf.
      4. Velegrakis, J.V. (2015). Operating System Mechanisms for Remote Resource Utilization in ARM Microservers. 2015.TR452_Operating_System_Mechanisms_ARM_Microservers.pdf.
      5. Kallimanis, N., & Fatourou, P. (2014). The Power of Scheduling-Aware Synchronization. 2014.TR442_Scheduling-Aware_Synchronization.pdf.
      6. Sfakianakis, Y.S, Mavridis, S., Fountoulakis, M., Papageorgiou, S.P, Chasapis, K., Papagiannis, A., Marazakis, M., & Bilas, A. (2014). Vanguard:Increasing Server Utilization via Workload Isolation in the Storage I/O Path. TR446_Vanguard_Increasing_Server_Utilization_Storage.pdf.
      7. Lyberis, S. (2013). Myrmics: A Scalable Runtime System for Global Address Spaces. 2013.TR436_Myrmics_Scalable_Runtime_System_Global_Address_Spaces.pdf.
      8. Bushkov, V.B, Fatourou, P., & Dziuma, D.D, Guerraoui, R.G (2013). Snapshot Isolation Does Not Scale Either. 2013.TR437_Snapshot_Isolation_Does_Not_Scale_Either.pdf.
      9. Dziuma, D.D, Fatourou, P., & Kanellou, E.K. (2013). Survey on consistency conditions. 2013.TR439_Survey_on_Consistency_Conditions.pdf.
      10. Tzenakis, G., Papatriantafyllou, A., Zakkak, F. S., Vandierendonck, H., Pratikakis , P., & Nikolopoulos, D. (2012). BDDT: Block-level Dynamic Dependence Analysis for Deterministic Task-Based Parallelism. 2012 TR426_Block-level_Dynamic_Dependence_Analysis_for_Deterministic_Task-Based_Parallelism.pdf.
      11. Pratikakis , P., Chinis, G, Athanasopoulos, E., & Ioannidis, S. (2012). Practical Information Flow for Legacy Web Applications. 2012.TR428_Practical-Information_Flow_for_Legacy_Web_Applications.pdf.
      12. Lyberis, S., & Kalokairinos, G. (2012). The 512-core Formic Hardware Prototype : Architecture Manual & Programmer's Model. 2012.TR430_The_512-core_Formic_Hardware_Prototype.pdf.
      13. Passas, G. (2012). VLSI Micro-Architectures for High-Radix Crossbars. 2012.TR427_VLSI_Micro-Architectures_High-Radix_Crossbars.pdf.
      14. Tsaliagos, D. (2011). Design and Implementation of a Directory based Cache Coherence Protocol. 2011.TR418_Directory_based_Cache_Coherence_Protocol.pdf.
      15. Kavadias, S.G. (2010). Direct Communication and Synchronization Mechanisms in Chip Multiprocessors. 2010.TR411_Direct_Communication_Synchr_Mechanisms_Chip_Multiprocessors.pdf.
      16. Nikiforos, G. (2010). FPGA implementation of a cache controller with configurable scratchpad space. 2010.TR402_FPGA_Cache_Controller.pdf.
      17. Mihelogiannakis, G. (2007). Approaching Ideal NoC Latency with Pre-Configured Routes. 2007.TR391_Approaching_Ideal_NoC_Latency.pdf.
      18. Papamichael, M. (2007). Network Interface Architecture and Prototyping for Chip and Cluster Multiprocessors. 2007.TR392_Network_Interface_Architecture_Chip_Cluster_Multiprocessors.pdf.
      19. Chrysos, N.I. (2007). Request-Grant Scheduling for Congestion Elimination in Multistage Networks. 2007.TR388_Congestion_Elimination_Multistage_Networks.pdf.
      20. Apostolopoulos, G. (2006). Building Extensible and Robust Networking Systems using Virtual Machines. 2006.TR384_Extensible_Robust_Networking_Systems.pdf.
      21. Vlachos, E. (2006). Design and Implementation of a Coherent Memory Sub-System for Shared Memory Multiprocessors. 2006.TR382_Coherent_Memory_Sub-System_Multiprocessors.pdf.
      22. Kalokairinos, G., Papaefstathiou, V., Ioannou, A., Simos, D.G., Papamichail, M., Mihelogiannakis, G., Marazakis, M., Pnevmatikatos, D., & Katevenis, M.G.H. (2006). Design and Implementation of a Multi-Gigabit NIC and a Scalable Buffered Crossbar Switch. 2006.TR376_Design_Multi-Gigabit_NIC.pdf.
      23. Apostolopoulos, G., & Ciurea, I. (2006). Reducing the Forwarding State Requirements of Point-to-Multipoint Trees Using MPLS Multicast. 2006.TR367_Reducing_Requirements_Point-to-Multipoint_Trees.pdf.
      24. Flouris, M.D., Lachaize, R., & Bilas, A. (2006). Shared & Flexible Block I/0 for Cluster-Based Storage. 2006.TR380_Shared_Flexible_Block_Cluster-Based_Storage.pdf.
      25. Apostolopoulos, G. (2006). Using Multiple Topologies for IP-only Protection Against Network Failures: A Routing Performance Perspective. 2006.TR377_Routing_Performance_Perspective.pdf.
      26. Apostolopoulos, G., & Chasapis, K. (2006). V-eM: A Cluster of Virtual Machines for Robust, Detailed, and High-Performance Network Emulation. 2006.TR371_V-eM_Cluster_of_Virtual_Machines.pdf.
      27. Matthaiakis, P. (2005). Study of the inter and intra die variability of the SPARTAN 2E FPGA using dual rail circuits. 2005.TR361_Spartan_2E_FPGA_using_dual_rail_circuits.pdf.
      28. Kounalakis, E. (2005). The Mythical IP Block: An Investigation of Contemporary IP Characteristics. 2005.TR366.Mythical_IP_Block.pdf.
      29. Andrikos, N. (2004). Automated Flow for Digital Circuits De-synchronization. 2004.TR338_Automated_Flow_for_Digital_Circuits_De-synchronization.pdf.
      30. Simos, D.G. (2004). Design of a 32x32 Variable-Packet-Size Buffered Crossbar Switch Chip. 2004.TR339_Variable_Packet-Size_Buffered_Crossbar_Switch_Chip.pdf.
      31. Vlachos, E. (2004). Study of asynchronous controllers" circuits in de-synchronized systems. 2004.TR337_Asynchronous_Controllers"_Circuits.pdf.
      32. Flouris, M.D., & Bilas, A. (2004). Violin: A Framework for Extensible Block-level Storage. 2004.TR344_Violin_Framework_Extensible_Block-level_Storage.pdf.
      33. Kokkalis, N.P. (2003). A Switching Fabric Simulator Accelerator using a systolic array of FPGA"s. 2003.TR321.Switching_Fabric_Simulator_Accelerator_using.FPGAs.pdf.
      34. Flouris, M.D., & Bilas, A. (2003). Clotho: Transparent Data Versioning at the Block I/O Level. 2003.TR326_Clotho_Transparent_Data_Versioning.pdf.
      35. Chrysos, N.I. (2003). Design Issues of Variable-Packet-Size, Multiple-Priority Buffered Crossbars. 2003.TR325_Multiple-priority_Buffered_Crossbars.pdf.
      36. Passas, G. (2003). Performance Evaluation of Variable Packet Size Buffered Crossbar Switches. 2003.TR328_Evaluation_Packet-Size_Buffered_Crossbar_Switches.pdf.
      37. Antonatos, S., Anagnostakis, K.G., Markatos, E.P., & Polychronakis, M. (2002). Benchmarking and Design of String Matching Intrusion Detection Systems. 2002.TR315.benchmarking_ids.ps.gz.
      38. Sapountzis, G., & Katevenis, M.G.H. (2002). Benes Fabrics with Internal Backpressure: First Work-in-Progress Report. 2002.TR303.Benes_Fabrics_Internal_Backpressure.ps.gz.
      39. Sapountzis, G. (2002). Benes Switching Fabrics with 0(N)-Complexity Internal Backpressure. 2002.TR316.Bennes_Switching_Fabrics_Complexity_Internal_Backpressure.pdf.gz.
      40. Kapsalis, D. (2002). Design and implementation of a per-flow queue manager for an ATM switch using FPGA Technology. 2002.TR302.Design_per_flow_queue_manager_FPGA_Technology.ps.gz.
      41. Sotiriou, Ch.P. (2002). Direct-Mapped Asynchronous Finite-State Machines in CMOS Technology. 2002.TR305.Direct-Mapped_Asynchronous_CMOS_Technology.pdf.gz.
      42. Anagnostakis, K.G., Antonatos, S., Markatos, E.P., & Polychronakis, M. (2002). E2 XB: A Domain-Specific String Matching Algorithm for Intrusion Detection. 2002.TR311.Domain_String_Matching_Algorithm_Intrusion_Detection.ps.gz.
      43. Markatos, E.P., Antonatos, S., Polychronakis, M., & Anagnostakis, K.G. (2002). Exclusion-based signature matching for intrusion detection. 2002.TR310.String_Matching_for_Intrusion_Detection.ps.gz.
      44. Sotiriou, Ch.P. (2002). Implementing Asynchronous Circuits using a Conventional EDA Tool-Flow. 2002.TR306.Asynchronous_Circuits_using_Conventional_EDA_Tool-Flow.pdf.gz.
      45. Portokalidis, G., Markatos, E.P., & Marazakis, M. (2002). Study and Bridging of Peer-to-Peer File Sharing Systems. 2002.TR312.Bridging_Peer-to-Peer_File_Sharing_Systems.pdf.gz.
      46. Chrysos, N.I., & Katevenis, M.G.H. (2002). Weighted Max-Min Fair Scheduling for an Input-Buffered Crossbar Switch, with Small Internal Memory. 2002.TR309.Max_Min_Fair_Scheduling_Input_Buffered_Crossbar_Switch.ps.gz.
      47. Markatos, E.P. (2001). Speeding up TCP / IP : Faster Processors are not Enough. 2001.TR297.SpeedingUp_TCP_IP_faster_processors.ps.gz.
      48. Markatos, E.P. (2001). Tracing a large-scale Peer to Peer System: an hour in the life of Gnutella. 2001.TR298.Tracing_Peer_to_Peer_System.ps.gz.
      49. Ioannou, A. (2000). An ASIC Core for Pipelined Heap Management to Support Scheduling in High Speed Networks. 2000.TR278.ASIC_Core_Pipelined_Heap_High_Speed_Networks.ps.gz.
      50. Markatos, E.P., Pnevmatikatos, D., Flouris, M.D., & Katevenis, M.G.H. (2000). Web-Conscious Storage Management for Web Proxies. 2000.TR275.Web-Conscious_Storage_Management_Web-Proxies.ps.gz.
      51. Katehakis, D.G., Chalkiadakis, G., Tsiknakis, M.N., & Orphanoudakis, S.C. (1999). A distributed, agent-based architecture for the acquisition, management, archiving and display of real-time monitoring data in the intensive care unit.. 1999.TR261.Intensive-Care_CORBA_SoftwareAgents_real-time-ICU-monitoring.ps.gz.
      52. Dollas, A., Papadimitriou, K., Mathioudakis, C., Markatos, E.P., & Katevenis, M.G.H. (1999). Experimental ATM Network Interface Performance Evaluation. 1999.TR244.ATM_if_perf.ps.gz.
      53. Mavroidis, I. (1999). Hardware Implementation of a Routine Filter to support Wormhole IP over ATM. 1999.TR258.RoutingFilterCore.ps.gz.
      54. Sapountzis, G. (1999). Routing Table Organization and Management in the Wormhole IP Routing Filter. 1999.TR257.RTOrgMng.ps.gz.
      55. Markatos, E.P. (1998). A Cash-based Approach to Caching Web Documents. 1998.TR230.cash_based_caching.ps.gz.
      56. Katevenis, M.G.H., Serpanos, D.N., & Spyridakis, E. (1998). Credit-Flow-Controlled ATM for MP Interconnection: the ATLAS I Single-Chip ATM Switch. 1998.HPCA.atlas4mp.ps.gz.
      57. Glykopoulos, G. (1998). Design and Implementation of a 1.2 Gbit/s ATM Cell Buffer using a Synchronous DRAM chip. 1998.TR221.ATM_Cell_Buffer_using_SDRAM.ps.gz.
      58. Mavroidis, I. (1998). Heap Management in Hardware. 1998.TR222.Heap_Management_in_Hardware.ps.gz.
      59. Kornaros, G., Pnevmatikatos, D., Vatsolaki, P., Kalokairinos, G., Xanthaki, Ch., Mavroidis, D., Serpanos, D.N., & Katevenis, M.G.H. (1998). Implementation of ATLAS I: a Single-Chip ATM Switch with Backpressure. 1998.HOTI.atlasIimpl.ps.gz.
      60. Papathanasiou, A E., & Markatos, E.P. (1998). Lightweight Transactions on Networks of Workstations. 1998.ICDCS.ps.gz.
      61. Ioannidis, S., Markatos, E.P., & Sevaslidou, J.E. (1998). On Using Network Memory to Improve the Performance of Transaction -Based Systems. 1998.PDTA.RVM_EXODUS.ps.gz.
      62. Pnevmatikatos, D., Markatos, E.P., Magklis, G.I., & Ioannidis, S. (1998). On Using Network RAM as a non-volatile Buffer. 1998.TR227.NVRAM.ps.gz.
      63. Flouris, M.D., & Markatos, E.P. (1998). The Network RamDisk : Using Remote Memory on Heterogeneous NOWs. 1998.TR226.nrd_TR.ps.gz.
      64. Markatos, E.P., Katevenis, M.G.H., & Vatsolaki, P. (1998). The Remote Enqueue Operation on Networks of Workstations. 1998.CANPC98.REQ.ps.gz.
      65. Katevenis, M.G.H., Vatsolaki, P., Serpanos, D.N., & Markatos, E.P. (1997). ATLAS I: A Single-chip ATM switch for NOWs. 1997.CANPC97.ATLAS.ps.gz.
      66. Katevenis, M.G.H. (1997). Buffer Requirements of Credit-Based Flow Control when a Minimum Draining Rate is Guaranteed. 1997.HPCS97.drain_cr_buf.ps.gz.
      67. Markatos, E.P., Katevenis, M.G.H., Kalokairinos, G., Magklis, G.I., Milolidakis, G., & Oikonomou, Th. (1997). Issues in the Design and Implementation of User-Level DMA. 1997.TR182.UDMA.ps.gz.
      68. Papathanasiou, A E., & Markatos, E.P. (1997). Lightweight Transactions on Networks of Workstations. 1997.TR209.Lightweight_Transactions_on_NOWs.ps.gz.
      69. Katevenis, M.G.H., Serpanos, D.N., & Markatos, E.P. (1997). Multi-Queue Management and Scheduling for Improved QoS in Communication Networks. 1997.EMMSEC.Muqpro.ps.gz.
      70. Ioannidis, S., Markatos, E.P., & Sevaslidou, J.E. (1997). On using Network Memory to Improve the Performance of Transaction-Based Systems. 1997.TR190.Remote_memory_RVM.ps.gz.
      71. Kornaros, G., Kozyrakis, Ch., Vatsolaki, P., & Katevenis, M.G.H. (1997). Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control. 1997.ARVLSI.Pipe_MultiQueue.ps.gz.
      72. Artavanis, M. (1997). Simulation of the Shared Disks Architecture for Transaction Processing Systems. 1997.TR211.Simulation_SharedDisks_Archit_Transaction_Processing_Systems.ps.gz.
      73. Katevenis, M.G.H., Serpanos, D.N., & Spyridakis, E. (1997). Switching Fabrics with Internal Backpressure using the ATLAS I Single-Chip ATM Switch. 1997.GLOBECOM.ATLAS_I_Fabrics.ps.gz.
      74. Markatos, E.P., & Katevenis, M.G.H. (1997). User-Level DMA without Operating System Kernel Modification. 1997.HPCA97.user_level_dma.ps.gz.
      75. Markatos, E.P. (1997). Visualizing Working Sets. 1997.TR192.Visualizing_working_sets.ps.gz.
      76. Markatos, E.P., & Chronaki, C. (1996). A Top-10 Approach to Prefetching on the Web. 1996.TR173.Web_Prefetching.ps.gz.
      77. Nikolaou, Ch., Markatos, E.P., Karavassili, M., & Saridakis, T. (1996). ArrayTracer: A Parallel Performance Analysis Tool. 1996.TR162.ArrayTracer_A_Parallel_Performance_Analysis_Tool.ps.gz.
      78. Katevenis, M.G.H., Serpanos, D.N., & Vatsolaki, P. (1996). ATLAS I: A General-Purpose, Single-Chip ATM Switch with Credit-Based Flow Control. 1996.HOTI.ATLAS_I_ATMswitchChip.ps.gz.
      79. Katevenis, M.G.H., & Vatsolaki, P. (1996). ATLAS I: A Single-Chip ATM Switch with HIC Links and Multi-Lane Back-Pressure. 1996.EMSYS96.ATLAS_I_ATMswitchHIC.ps.gz.
      80. Spyridakis, E. (1996). Comparison of Credit Based ATM and Wormhole Under Bursty Traffic or With Hot Spots. 1996.TR170.ATM_vs_Wormhole_in_Greek.ps.gz.
      81. Katevenis, M.G.H., Vatsolaki, P., & Chalkiadakis, V. (1996). Credit-Flow-Controlled ATM over HIC Links in the ASICCOM ''ATLAS I"" Single-Chip Switch. 1996.RTMagazine.ATLAS_I_ATMswitchChip.ps.gz.
      82. Katevenis, M.G.H., Serpanos, D.N., & Spyridakis, E. (1996). Credit-Flow-Controlled ATM versus Wormhole Routing. 1996.TR171.ATM_vs_Wormhole.ps.gz.
      83. Markatos, E.P., & Dramitinos, G. (1996). Implementation of a Reliable Remote Memory Pager. 1996.usenix.ps.gz.
      84. Markatos, E.P. (1996). Issues in Reliable Network Memory Paging. 1996.MASCOTS96.Reliable_Network_Memory.ps.gz.
      85. Markatos, E.P., & Katevenis, M.G.H. (1996). Telegraphos :High-Performance Networking for Parallel Processing on Workstation Clusters.. 1996.HPCA96.Telegraphos.ps.gz.
      86. Kozyrakis, Ch. (1996). The Architecture, Operation, and Design of the Queue Management Block in the ATLAS I ATM Switch. 1996.TR172.QueueManagement.ps.gz.
      87. Markatos, E.P. (1996). Using Remote Memory to avoid Disk Thrashing: A Simulation Study. 1996.MASCOTS96.Remote_memory_paging.ps.gz.
      88. Efthymiou, A. (1995). Design, Implementation, and Testing of a 25 Gb/s Pipelined Memory Switch Buffer in Full-custom CMOS. 1995.TR143.Design_Implementation_25Gbs_PipelinedMem_Switch_Buffer.ps.gz.
      89. Markatos, E.P., Dramitinos, G., & Papachristos, K. (1995). Implementation and Evaluation of a Remote Memory Pager. 1995.TR129.remote_memory_paging.ps.gz.
      90. Labrinidis, A. (1995). Methods to cluster transactions into utilization classes with similar workload characteristics. 1995.TR135.Methods_cluster_transactions_similar_workload_characteristics.ps.gz.
      91. Katevenis, M.G.H., Vatsolaki, P., & Efthymiou, A. (1995). Pipelined Memory Shared Buffer for VLSI Switches. 1995.SIGCOMM95.PipeMemoryShBuf.ps.gz.
      92. Katevenis, M.G.H., Vatsolaki, P., Efthymiou, A., & Stratakis, M. (1995). VC-level Flow Control and Shared Buffering in the Telegraphos Switch. 1995.HOTI.VCflowCtrlTeleSwitch.ps.gz.
      93. Xanthaki, Z. (1994). A Memory Controller for Access Interleaving over a single Rambus. 1994.TR124.RAMBUS_AccessInterleaving_MemoryController.ps.gz.
      94. Chatzaki, M. (1994). A Translation Scheme Between Two Real-Time Formalisms. 1994.TR128.specification_automatic_verification_timed_automata.ps.gz.
      95. Dimitriadis, G. (1994). An Arithmetic Entropy Codec VLSI chip for JPEG Image Compression. 1994.TR114.Arithmetic_Entropy_Codec_VLSI_chip_for_JPEG.ps.gz.
      96. Katevenis, M.G.H. (1994). FORTH, ICS: Computer Architecture and VLSI Systems Group: A Profile. 1994.AVG_PROFILE.ps.Z.
      97. Katevenis, M.G.H., Vatsolaki, P., & Efthymiou, A. (1994). Pipelined Memory Organization for High Performance Switching and Buffering. 1994.TR127.PipelinedMemory.ps.Z.
      98. Katevenis, M.G.H. (1994). Telegraphos: High-Speed Communication Architecture for Parallel and Distributed Computer Systems. 1994.TR123.Telegraphos.ps.Z.
      99. Markatos, E.P., & Chronaki, C. (1994). Using reference counters in Update Based Coherent Memory. 1994.PARLE94.Reference_Counters.ps.Z.
      100. Markatos, E.P. (1993). How Architecture Evolution Influences the Scheduling Discipline used in Shared-Memory Multiprocessors. 1993.PARCO93.Architecture_infuence_on_Scheduling.ps.Z.
      101. Markatos, E.P., & Leblanc, Th.J. (1993). Locality-Based Scheduling in Shared-Memory Multiprocessors. 1993.TR94.Locality_Based_Scheduling.ps.Z.
      102. Markatos, E.P., & Chronaki, C. (1993). Trace-Driven Simulation of Data-Alignment and other Factors affecting Update and Invalidate Based Coherent Memory. 1993.TR93.DATA_ALIGNMENT_IN_VIRTUAL_SHARED_MEMORY.ps.Z.
      103. Markatos, E.P., & LeBlanc, T.J. (1993). Using Processor Affinity in Loop Scheduling on Shared-Memory Multiprocessors. 1993.TPDS.Affinity_Loop_Scheduling.ps.Z.
      104. Vatsolaki, P. (1992). Design of a High-Speed UART VLSI Library Cell. 1992.TR50.High_Speed_UART_VLSIlibCell.ps.Z.
      105. Sidiropoulos, S. (1991). A General Purpose ATM Switch Chip : Architecture and Feasibility Study. 1991.TR025_General_Purpose_ATM_Switch_Chip.pdf.
      106. Sidiropoulos, S. (1991). Fast Packet Switches for Asynchronous Transfer Mode. 1991.TR25.Fast_packet_switches.ps.Z.
      107. Katevenis, M.G.H. (1987). Fast Switching and Fair Control of Congested Flow in Broad-Band Networks. 1987.TR001_Fast-Switching_Fair-Control_Broad-Band-Networks.pdf.
              Found: 107 publications
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