ICS Publications - CARV

Conferences (257)

    Papers in Proceedings (full-paper reviewed)

  1. Syrivelis, D., Reale, A., Katrinis, K., Syrigos, I. , Bielski , M., Theodoropoulos, D., Pnevmatikatos, D., & Zervas, G. (2017). A Software-defined Architecture and Prototype for Disaggregated Memory Rack Scale SystemsInternational Conference On Embedded Computer Systems: Architectures, Modeling And Simulation (SAMOS 2017) , Samos, Greece, 17-20 July (pp. 1-8).
  2. Bozikas, D., Alachiotis , N., Pavlidis , P., Sotiriades, E., & Dollas, A. (2017). Deploying FPGAs to Future-proof Genome-wide Analyses based on Linkage Disequilibrium. 26th International Conference on Field Programmable Logic and Applications (FPL 2017),  Ghent, Belgium, 4 - 8 September .
  3. Katsogridakis , P., Papagiannaki, S., & Pratikakis , P. (2017). Execution of Recursive Queries in Apache SparkEuro-Par 2017: Parallel Processing: 23rd International Conference on Parallel and Distributed Computing, Santiago de Compostela, Spain, August 28 – September 1 (vol. 10417 LNCS, pp. 289-302). Springer .
  4. Theodoropoulos, D., Alachiotis , N., & Pnevmatikatos, D. (2017). FPGA-based Evaluation Platform for Disaggregated ComputingInternational Conference On Embedded Computer Systems: Architectures, Modeling And Simulation (SAMOS 2017), Samos, Greece, 17-20 July (pp. 1-8).
  5. Mouzakitis, A., Pinto, C., Nikolaev, N., Rigo, A., Raho, D., Aronis, B., & Marazakis, M. (2017). Lightweight and Generic RDMA Engine Para-Virtualization for the KVM HypervisorProceedings of the 2017 International Conference on High Performance Computing & Simulation (HPCS 2017) , Genoa, Italy, 17-21 July 2017 (pp. 17-21). IEEE.
  6. Vasilakis, E., Sourdis, I., Papaefstathiou, V., Psathakis, A., & Katevenis , M. (2017). Modeling Energy-Performance Tradeoffs in ARM big.LITTLE Architectures. Proceedings of the 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) , Thessaloniki, Greece, 25 - 27 September.
  7. Malek, A., Vasilakis, E., Papaefstathiou, V., Trancoso, P., & Sourdis, I. (2017). Odd-ECC: On-demand DRAM Error Correcting Codes. Proceedings of the International Symposium on Memory Systems (MEMSYS ), Washington DC, USA, 2-5 October .
  8. Rigo, A., Pinto, C., Pouget, K., Raho, D., Dutoit, D., Martinez, P.Y., Doran, Ch., Benini, L., Mavroidis, I., Marazakis, M., Bartsch, V., Lonsdale, G., Pop, A. , Goodacre, J., Colliot, A. , Carpenter, P., & Radojković, P. , Pleiter, D. , Drouin, D. , de Dinechin, B.D.  (2017). Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach2017 Euromicro Conference on Digital System Design (DSD), Vienna, Austria, 30 Aug.-1 Sept. (pp. 486-493). IEEE.
  9. Drumond, M., Daglis, A., Mirzadeh, N., Ustiugov, D., Picorel, J., Falsafi, B., Grot, B., & Pnevmatikatos, D. (2017). The Mondrian Data EngineProceedings of the 44th Annual International Symposium on Computer Architecture (ISCA '17 ), Toronto, ON, Canada, June 24 - 28 (pp. 639-651 ). ACM.
  10. Mazumdar, S., Ayguade, E., Bettin, N., Bueno, J., Ermini, S., Filgueras, A, Jimenez-Gonzalez, D., Alvarez-Martinez, C., Martorell, X., Montefoschi, F., Oro, D., Pnevmatikatos, D., Rizzo, A., Theodoropoulos, D., & Giorgi , R. (2016). AXIOM: A Hardware-Software Platform for Cyber Physical Systems19th Euromicro Conference on Digital System Design (DSD 2016), Limassol, Cyprus, 31 Aug.-2 Sept. (pp. 539-546). IEEE.
  11. Zakkak, F. S., & Pratikakis , P. (2016). Building a Java™ Virtual Machine for Non-Cache-Coherent Many-core ArchitecturesProceedings of the 14th International Workshop on Java Technologies for Real-time and Embedded Systems (JTRES 2016) , Lugano, Switzerland , August 29 - September 02. ACM.
  12. Zakkak, F. S., & Pratikakis , P. (2016). DiSquawk: 512 cores, 512 memories, 1 JVMProceedings of the 13th International Conference on Principles and Practices of Programming on the Java Platform: Virtual Machines, Languages, and Tools (PPPJ '16), Lugano, Switzerland, 29 Aug. - 2 Sep. (12 pages). ACM.
  13. Fatourou, P., Kallimanis, N., Kanellou, E.K., Makridakis, O., & Symeonidou, C. (2016). Efficient Distributed Data Structures for Future Many-core ArchitecturesProceedings of the 22nd International Conference on Parallel and Distributed Systems (ICPADS 2016), Wuhan, China, 13-16 December (pp. 835-842). IEEE.
  14. Marazakis, M., Goodacre, J., Fuin, D., Carpenter, P., Thomson, J., Matus, E., Bruno, A., Stenstrom, P., Martin, J., Durand, Y., & Dor, I.  (2016). EUROSERVER: Share-Anything Scale-Out Micro-Server DesignProceedings of the Design, Automation, and Test in Europe Conference (DATE 2016), Dresden, Germany, 14-18 March (pp. 678-683). IEEE.
  15. Papakonstantinou, N., Zakkak, F. S., & Pratikakis , P. (2016). Hierarchical Parallel Dynamic Dependence Analysis for Recursively Task-Parallel Programs30th IEEE International Parallel & Distributed Processing Symposium (IEEE IPDPS 2016), Chicago, IL, USA, 23-27 May . IEEE.
  16. Pavlidakis, E., Mavridis, S., Saloustros, G., & Bilas, A. (2016). KVFS: An HDFS Library over NoSQL DatabasesProceedings of the 6th International Conference on Cloud Computing and Services Science - Volume 1 and 2, Rome, Italy, April 23-25 (pp. 360-367). ACM.
  17. Katrinis, K., Zervas, G., Pnevmatikatos, D., Syrivelis, D., Alexoudi, T., Theodoropoulos, D., Raho, D., Pinto, C., Espina, F., Lopez-Buedo, S., Chen, Q., Nemirovsky, M., Roca, D. , Klos, H., & Berends, T. (2016). On interconnecting and orchestrating components in disaggregated data centers: The dReDBox project visionEuropean Conference on Networks and Communications (EuCNC 2016), Athens, Greece, 27-30 June (pp. 235-239). IEEE.
  18. Katrinis, K., Syrivelis, D., Pnevmatikatos, D., Zervas, G., Theodoropoulos, D., Koutsopoulos, I., Hasharoni, K., Raho, D., Pinto, C., Espina, F., Lopez-Buedo, S., Chen, Q., Nemirovsky, M., Roca, D. , Klos, H., & Berends, T. (2016). Rack-scale disaggregated cloud data centers: The dReDBox project visionProceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, 14-18 March (pp. 690-695). IEEE.
  19. Katevenis , M., Chrysos, N., Marazakis, M., Mavroidis, I., Chaix, F., Kallimanis, N., J. Navaridas, J. , Goodacre, J., Vicini, P. , Biagioni, A., Paolucci, P. S. , Lonardo, A. , Pastorelli, E. , Lo Cicero, F. , Ammendola, R. , Hopton, P., Coates, P., Taffoni, G., Cozzini, S., Kersten, M., Zhang, Y., Sahuquillo, J., Lechago, S. , Pinto, C., Lietzow, B., Everett, D., & Perna, G.  (2016). The ExaNeSt Project: Interconnects, Storage, and Packaging for Exascale Systems19th Euromicro Conference on Digital System Design (DSD 2016), Limassol, Cyprus, 31 Aug.-2 Sept. (pp. 60-67). IEEE.
  20. Papagiannis, A., Saloustros, G., Gonzalez-Ferez, P., & Bilas, A. (2016). Tucana: design and implementation of a fast and efficient scale-up key-value storeProceedings of the 2016 USENIX Annual Technical Conference (USENIX ATC '16), Denver, CO, USA, June 22-24 (pp. 537-550). ACM.
  21. Charitopoulos, G., Pnevmatikatos, D., Santambrogio, M.D., Papadimitriou, K., & Pau, D. (2015). A run-time system for partially reconfigurable FPGAs: The case of STMicroelectronics SPEAr board. PARCO 2015, Edinburgh, Scotland, UK, 1–4 September (pp. 553-562).
  22. Psathakis, A., Papaefstathiou, V., Chrysos, N., Chaix, F., Vasilakis, E., Pnevmatikatos, D., & Katevenis , M. (2015). A systematic evaluation of emerging mesh-like CMP NoCsANCS '15 Proceedings of the Eleventh ACM/IEEE Symposium on Architectures for networking and communications systems, Oakland, CA USA, 7-8 May (pp. 159-170).
  23. Charitopoulos, G., , , Papadimitriou, K., & Pnevmatikatos, D. (2015). Hardware Task Scheduling for Partially Reconfigurable FPGAsApplied Reconfigurable Computing: 11th International Symposium (ARC 2015), Lecture Notes in Computer Science, Bochum, Germany, April 13-17 (vol. 9040, pp. 487-498). Springer.
  24. Gonzalez-Ferez, P., & Bilas, A. (2015). Reducing CPU and network overhead for small I/O requests in network storage protocols over raw Ethernet 31st Symposium on Mass Storage Systems and Technologies (MSST 2015), Santa Clara, California, USA, 30 May - 5 June (pp. 1-12). (pdf).
  25. Saloustros, G., & Magoutis, K. (2015). Rethinking HBase: Design and Implementation of an Elastic Key-Value Store over Log-Structured Local Volumes14th International Symposium on Parallel and Distributed Computing (ISPDC 2015) ,  Limassol, Cyprus, 29 June - 2 July (pp. 225 - 234).
  26. Theodoropoulos, D., Pnevmatikatos, D., Alvarez , C., Ayguade, E., Bueno, J., Filgueras, A, Jimenez-Gonzalez, D., Martorell, X., Navarro, N., Segura , C., Fernandez, C., Oro, D., Rodriguez Saeta, J., Gai, P., Rizzo, A., & Giorgi , R. (2015). The AXIOM project (Agile, eXtensible, fast I/O Module)International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XV), Samos, Greece, 20-23 July (pp. 262 -269). IEEE.
  27. Alvarez , C., Ayguade, E., Bueno, J., Filgueras, A, Jimenez-Gonzalez, D., Martorell, X., Segura , C., Fernandez, C., Oro, D., Rodriguez Saeta, J., Passera, P., Pomella, A., Rizzo, A., & Giorgi , R. (2015). The AXIOM Software Layers18th Euromicro Conference on Digital Systems Design (DSD), Funchal, Madeira, Portugal, 26-28 Aug. (pp. 117 -124). IEEE.
  28. Kallimanis, N., & Kanellou, E.K. (2015). Wait-free Concurrent Graph Objects with Dynamic TraversalsOPODIS 2015 : 19th International Conference on Principles of Distributed Systems, Rennes, France, 14-17 Dec.
  29. Avni, H., Dolev, S., Fatourou, P., & Kosmas, E. (2014). Abort Free SemanticTM by Dependency Aware Scheduling of Transactional InstructionsNetworked systems : second International Conference (NETYS 2014), Lecture Notes in Computer Science ,  May 2014 (vol. 8593, pp. 25-40). Marrakech; Morocco: Springer.
  30. Fatourou, P., & Kallimanis, N. (2014). Brief Announcement: The Power of Scheduling-Aware Synchronization. Distributed computing : 28th International Symposium (DISC 2014), Lecture Notes in Computer Science , Austin, Texas, October 2014 (vol. 8784, pp. 533-535). Springer.
  31. Psathakis, A., Papaefstathiou, V., Katevenis, M.G.H., & Pnevmatikatos, D. (2014). Design space exploration for fair resource-allocated NoC architecturesInternational Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Samos, Greece, 14-17 July (pp. 141-148). IEEE.
  32. Sourdis, I., Strydis, C., Armato , A., Bouganis, C.S., Falsafi, B., Gaydadjiev, G.N., Isaza, S., Malek, A., Mariani, R., Pagliarini, S., Pnevmatikatos, D., Pradhan , D.K., Rauwerda, G., Seepers, R.M., Shafik, R.A., Smaragdos , G., Theodoropoulos, D., Tzilis, S., & Vavouras, M. (2014). DeSyRe: On-Demand Adaptive and Reconfigurable Fault-Tolerant SoCsReconfigurable Computing: Architectures, Tools, and Applications 10th International Symposium (ARC 2014), Vilamoura, Portugal, April 14-16 (vol. 8405 LNCS, pp. 312-317). Springer .
  33. Durand, Y., Carpenter, P. M., Adami, S., Bilas, A., Dutoit, D., Farcy, A., Gaydadjiev, G., Goodacre, J., Katevenis, M.G.H., Marazakis, M., Matus, E., Mavroidis, I., & Thomson, J. (2014). EUROSERVER: Energy Efficient Node for European Micro-servers17th Euromicro Conference on Digital System Design (DSD), 2014, Verona, Italy, 27-29 August (pp. 206-213). IEEE.
  34. Zakkak, F. S., & Pratikakis , P. (2014). JDMM: a java memory model for non-cache-coherent memory architecturesISMM '14 : proceedings of the 2014 ACM SIGPLAN International Symposium on Memory Management, Edinburgh, Scotland, UK, June 12 (pp. 83-92 ). ACM.
  35. Mavridis, S., Sfakianakis, I., Papagiannis, A., Marazakis, M., & Bilas, A. (2014). Jericho: Achieving Scalability Through Optimal Data Placement on Multicore SystemsProceedings of the 2014 30th Symposium on Mass Storage Systems and Technologies (MSST 2014), Santa Clara, CA, USA, June 2-6. IEEE Computer Society.
  36. Katsogridakis , P., & Pratikakis , P. (2014). Micro-checkpointing in fault tolerant runtimesProceedings of the 11th ACM Conference on Computing Frontiers (CF '14 ), Cagliari, Italy , May 20-22 (pp. Article No.13 ). ACM.
  37. Fragkoulis, M., Spinellis, D, Louridas, P., & Bilas, A. (2014). Relational access to Unix kernel data structuresProceedings of the Ninth European Conference on Computer Systems (EuroSys '14), Amsterdam, The Netherlands, April 13 - 16. ACM.
  38. Ellen, F., Fatourou, P., Helga, J., & Ruppert, E. (2014). The amortized complexity of non-blocking binary search treesProceedings of the 2014 ACM symposium on Principles of distributed computing (PODC 2014), Paris, France, July 2014 (pp. 332-340). ACM Press.
  39. Bushkov, V.B, Dziuma, D.D, Fatourou, P., & Guerraoui, R.G (2014). The PCL theorem: transactions cannot be parallel, consistent and liveProceedings of the 26th ACM symposium on Parallelism in algorithms and architectures (SPAA '14) , June 2014 (pp. 178-187). Prague, Czech Republic: ACM Press.
  40. Gonzalez-Ferez, P., & Bilas, A. (2014). Tyche: An efficient Ethernet-based protocol for converged networked storage30th Symposium on Mass Storage Systems and Technologies (MSST 2014) , Santa Clara, CA, USA, 2-6 June (pp. 1-11). IEEE.
  41. Sfakianakis, Y.S, Mavridis, S., Papagiannis, A., Papageorgiou, S.P, Fountoulakis, M., Marazakis, M., & Bilas, A. (2014). Vanguard: Increasing Server Efficiency via Workload Isolation in the Storage I/O PathProceedings of the ACM Symposium on Cloud Computing (SOCC '14) , Seattle, WA, USA, November 03-05 (pp. 1-13). ACM.
  42. Fatourou, P., Kanellou, E.K., Kosmas, E., & Rabbi, M. F. (2014). WFR-TM: Wait-Free Readers Without Sacrificing Speculation of Writers18th International Conference on Principles of Distributed Systems (OPODIS 2014), Cortina d’Ampezzo, Ital, December 16-19 (vol. 8878 LNCS, pp. 420-436). Springer .
  43. Papaioannou, A., & Magoutis, K. (2013). An Architecture for Evaluating Distributed Application Deployments in Multi-CloudsProceedings of 5th IEEE International Conference on Cloud Computing Technology and Science (CloudCom 2013),  Bristol, UK, 2-5 December (pp. 547 -554).
  44. Chalkiadaki, M., & Magoutis, K. (2013). Managing Service Performance in the Cassandra Distributed Storage System Proceedings of 5th IEEE International Conference on Cloud Computing Technology and Science (CloudCom 2013), Bristol, UK, 2-5 December (pp. 64 -71).
  45. Zeginis, Ch., Kritikos, K., Garefalakis, P., Konsolaki, K., Magoutis, K., & Plexousakis, D. (2013). Towards Cross-Layer Monitoring of Multi-Cloud Service-Based Applications Kung-Kiu Lau, Winfried Lamersdorf, Ernesto Pimentel (Eds.): Service-Oriented and Cloud Computing. Second European Conference, ESOCC 2013, Málaga, Spain, September 11-13, 2013. Proceedings, Málaga, Spain(vol. 8135, pp. 188-195). (978-3-642-40650-8 (Print) 978-3-642-40651-5 (Online)).
  46. Tzenakis, G., Papatriantafyllou, A., Vandierendonck, H., Pratikakis , P., & Nikolopoulos, D.S. (2013). BDDT: Block-Level Dynamic Dependence Analysis for Task-Based ParallelismAdvanced parallel processing technologies : 10th International Symposium, APPT 2013, Stockholm, Sweden, August 27-28 (pp. 17-31). Springer.
  47. Symeonidou, C., Pratikakis , P., Bilas, A., & Nikolopoulos, D.S. (2013). DRASync: distributed region-based memory allocation and synchronizationEuroMPI '13 Proceedings of the 20th European MPI Users' Group Meeting, (pp. 49-54). ACM Press (978-1-4503-1903-4 ).
  48. Theodoropoulos, D., Pratikakis , P., & Pnevmatikatos, D. (2013). Efficient runtime support for embedded MPSoCsInternational Conference on Embedded Computer Systems, Architectures, Modeling, and Simulation : IC-SAMOS 2013, 15-18 July (pp. 164-171).
  49. Manousakis, I., Marazakis, M., & Bilas, A. (2013). FDIO: a feedback driven controller for minimizing energy in I/O-intensive applicationsProceedings of the 5th USENIX conference on Hot Topics in Storage and File Systems, (pp. 16). Berkeley, CA, USA: USENIX Association.
  50. Zakkak, F. S., Chasapis , D., Pratikakis , P., Bilas, A., & Nikolopoulos, D.S. (2013). Inference and Declaration of Independence in Task-Parallel ProgramsAdvanced Parallel Processing Technologies, Lecture Notes in Computer Science , (vol. 8299, pp. 1-16). Springer Berlin Heidelberg (978-3-642-45292-5).
  51. Papaefstathiou, V., Katevenis, M.G.H., Nikolopoulos, D.S., & Pnevmatikatos, D. (2013). Prefetching and Cache Management using Task LifetimesProceedings of the 27th international ACM conference on International conference on supercomputing (ICS '13), Eugene, Oregon, USA, 10-14 June (pp. 325-334). ACM Press.
  52. Mattheakis, P.M., Sotiriou, Ch.P., & Beerel, A. P. (2012). A Polynomial Time Flow for Implementing Free-Choice Petri-NetsProceedings of the 30th IEEE International Conference on Computer Design (ICCD 2012), Montreal, Quebec, Canada, September 30 - October 3 (pp. 227-234).
  53. Kitsos, G., Papaioannou, A., Tsikoudis, N., & Magoutis, K. (2012). Adapting Data-Intensive Workloads to Generic Allocation Policies in Cloud Infrastructures. IEEE Network Operations and Management Symposium (NOMS 2012), Maui, Hawaii, April 16-20 (pp. 25-33). IEEE.
  54. Pnevmatikatos, D., Becker, T., Brokalakis, A., Bruneel, K., Gaydadjiev, G., Luk, W., Papadimitriou, K., Papaefstathiou, I., Pell, O., Pilato, C., Robart, M., Santambrogio, M.D., Sciuto, D., Stroobandt, D., & Todman, T. (2012). FASTER: Facilitating Analysis and Synthesis Technologies for Effective ReconfigurationDSD 2012 : Proceedings, 15th Euromicro Conference on Digital System Design, 5-8 Sept. (pp. 234-241). IEEE.
  55. Lyberis, S., Kalokairinos, G., Ligerakis, M., Papaefstathiou, V., Tsaliagos, D., Katevenis, M.G.H., Pnevmatikatos, D., & Nikolopoulos, D.S. (2012). Formic: Cost-efficient and Scalable Prototyping of Manycore Architectures. Proc. of the 20th IEEE Int. Symposium on Field-Programmable Custom Computing Machines (FCCM'12), Toronto Canada, May 2012 (pp. 61-64).
  56. Garefalakis, P., & Magoutis, K. (2012). Improving Datacenter Operations Management Using Wireless Sensor Networks IEEE International Conference on Green Computing and Communications, Besançon, France, 20-23 Nov. (pp. 195-202). IEEE.
  57. Papadimitriou, K., Pilato, C., Pnevmatikatos, D., Santambrogio, M.D., Ciobanu, C.B., Todman, T., Becker, T., Davidson, T., Niu, X., Gaydadjiev, G., Luk, W., & Stroobandt, D. (2012). Novel Design Methods and a Tool Flow for Unleashing Dynamic Reconfiguration15th IEEE International Conference on Computational Science and Engineering : CSE 2012 , 5-7 Dec. (pp. 391-398). IEEE .
  58. Fatourou, P., & Kallimanis, N. (2012). Revisiting the combining synchronization technique. Proceedings of the 17th ACM SIGPLAN symposium on Principles and Practice of Parallel Programming (PPOPP '12), New Orleans, Louisiana, USA, (pp. 257-266). New York, NY, USA: ACM (978-1-4503-1160-1).
  59. Stamatakis, D., Tsikoudis, N., Smyrnaki, O., & Magoutis, K. (2012). Scalability of Replicated Metadata Services in Distributed File Systems. In Proceedings of 12th IFIP International Conference on Distributed Applications and Interoperable Systems (DAIS 2012), Stockholm, Sweden, June 14-15.
  60. Santambrogio, M.D., Pnevmatikatos, D., Papadimitriou, K., Pilato, C., Gaydadjiev, G., Stroobandt, D., Davidson, T., Becker, T., Todman, T., Luk, W., Bonetto, A., Cazzaniga , A., Durelli, G., & Sciuto, D. (2012). Smart technologies for effective reconfiguration: The FASTER approachReCoSoC : 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, 9-11 July (pp. 1-7). IEEE.
  61. Sourdis, I., Strydis, C., Bouganis, C.S., Falsafi, B., Gaydadjiev, G.N., Malek, A., Mariani, R., Pnevmatikatos, D., Pradhan , D.K., Rauwerda, G., Sunesen, K., & Tzilis, S. (2012). The DeSyRe Project: On-Demand System ReliabilityDSD 2012 : Proceedings, 15th Euromicro Conference on Digital System Design, 5-8 Sept. (pp. 335-342). IEEE.
  62. Lyberis, S., Pratikakis , P., Nikolopoulos, D.S., Schulz, M., Gamblin, T., & Supinski, B.R.de (2012). The myrmics memory allocator: hierarchical, message-passing allocation for global address spaces. Proceedings of the 2012 international symposium on Memory Management (ISMM 2012), Beijing, China, (pp. 15-24). New York, NY, USA: ACM (978-1-4503-1350-6).
  63. Akram, S., Marazakis, M., & Bilas, A. (2012). Understanding and Improving the Cost of Scaling Distributed Event Processing on Emerging Data-centric InfrastructuresProceedings of the 6th ACM International Conference on Distributed Event-Based Systems (DEBS'12), July 2012 (pp. 290-301). Berlin, Germany.
  64. Akram, S., Marazakis, M., & Bilas, A. (2012). Understanding scalability and performance requirements of I/O intensive applications on future multicore servers20th IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS 2012), August 7-9 (pp. 171-180). Arlington, Virginia, USA.
  65. Ellen, F., Fatourou, P., Kosmas, E., Milani, A., & Travers, C. (2012). Universal Constructions that Ensure Disjoint-Access Parallelism and Wait-Freedom. Proceedings of the 2012 ACM Symposium on Principles of Distributed Computing (PODC'12), July 16-18 (pp. 115-124). Madeira, Portugal 31st Annual ACM SIGACT-SIGOPS Symposium .
  66. Papagiannis, A., & Nikolopoulos, D.S. (2011). Scalable Runtime Support for Data Intensive Applications on the Single Chip Cloud Computer3rd Many-core Applications Research Community (MARC) Symposium, (pp. 25-30). KIT Scientific Publishing, Karlsruhe.
  67. Fatourou, P., & Kallimanis, N. (2011). A highly-efficient wait-free universal construction. Proceedings of the 23rd ACM symposium on Parallelism in algorithms and architectures, SPAA '11, San Jose, California, USA, (pp. 325-334). New York, NY, USA: ACM (978-1-4503-0743-7).
  68. Gao, Y., Kachris, C., & Katevenis, M.G.H. (2011). An Efficient Sequential Iterative Matching Algorithm for CIOQ Switches. Proc. of the 16th IEEE Symposium on Computers and Communications (ISCC 2011), Kerkyra (Corfu), Greece, 28 June - 1 July 2011 (pp. 558-563).
  69. Klonatos, Y., Makatos, A., Marazakis, M., Flouris, M.D., & Bilas, A. (2011). Azor: Using two-level block selection to improve SSD-based I/O caches. 6th IEEE International Conference on Networking, Architecture, and Storage (NAS 2011), July 28-30 (pp. 309-318). (pdf) (slides).
  70. Koromilas, L., & Magoutis, K. (2011). CassMail: A Scalable, Highly-Available, and Rapidly Prototyped Email Service. In Proceedings of 11th IFIP International Conference on Distributed Applications and Interoperable Systems (DAIS 2011), Reykjavik, Iceland, June 6-9. (pdf).
  71. Sebepou, Z., & Magoutis, K. (2011). CEC: Continuous Eventual Checkpointing for Data Stream Processing Operators. Proceedings of 41st IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2011), Hong Kong, China, June 27-30. (pdf).
  72. Kounalakis, E., & Sotiriou, Ch.P. (2011). CPlace: A Constructive Placer for Synchronous and Asynchronous Circuits. Proc. of the 17th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2011), Cornell Univ., Ithaca, NY, USA, 27-29 April.
  73. Alvanos, M., Tzenakis, G., Nikolopoulos, D.S., & Bilas, A. (2011). Design and Evaluation of a Task-based Parallel H.264 Video Encoder for Heterogenous Processors. In Proc. of the 2011 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XI), July 2011. (pdf).
  74. Tendulkar, P., Papaefstathiou, V., Nikiforos, G., Kavadias, S.G., Nikolopoulos, D.S., & Katevenis, M.G.H. (2011). Fine-Grain OpenMP Runtime Support with Explicit Communication Hardware Primitives. Proc. of the Design, Automation and Test in Europe (DATE 2011) , Grenoble, France, 14-18 March (pp. 891-894). (978-1-61284-208-0).
  75. Vandierendonck, H., Pratikakis , P., & Nikolopoulos, D.S. (2011). Parallel programming of general-purpose programs using task-based programming models. Proceedings of the 3rd USENIX conference on Hot topic in parallelism, HotPar'11, Berkeley, CA, (pp. 13-13). Berkeley, CA, USA: USENIX Association.
  76. Stamatakis, D., Grammenos, D., & Magoutis, K. (2011). Real-time Analysis of Localization Data Streams for Ambient Intelligence Environments. In Proceedings of International Joint Conference on Ambient Intelligence (AMI-11) , Amsterdam, The Netherlands, November 16-18 (pp. 92-97). (pdf).
  77. Kounalakis, E., & Sotiriou, Ch.P. (2011). SCPlace: A Statistical Slack-Assignment Based Constructive Placer. Proc. International Symposium on Quality Electronic Design (ISQED 2011), Santa Clara, CA, USA, 14-16 March .
  78. Kounalakis, E., Sotiriou, Ch.P., & Zebilis, V. (2011). Statistical Timing-based post-Placement Leakage Recovery. Proc. of the IEEE Annual Symposium on VLSI (IVLSI 2011), Chennai, India, 4-6 July 2011.
  79. Passas, G., Katevenis, M.G.H., & Pnevmatikatos, D. (2011). VLSI Micro-Architectures for High-Radix Crossbar Schedulers. Proc. 5th ACM/IEEE Int. Symp. on Networks-on-Chip (NOCS 2011), Pittsburgh, PA, USA, 1-4 May (pp. 217-224). (978-1-4503-0720-8).
  80. Papagiannis, A., & Nikolopoulos, D.S. (2010). Rearchitecting MapReduce for Heterogeneous Multicore Processors with Explicitly Managed MemoriesProc. of the 39th International Conference on Parallel Processing (ICPP), San Diego, California, September (pp. 121-130). (0190-3918).
  81. Passas, G., Katevenis, M.G.H., & Pnevmatikatos, D. (2010). A 128 × 128 × 24Gb/s crossbar interconnecting 128 tiles in a single hop and occupying 6%of their area. 4th ACM/IEEE International Symposium on Networks on Chip, NOCS 2010, Grenoble, France, 3-6 May (pp. 87-95). IEEE Computer Society (9780769540535).
  82. Uppoor, S., Flouris, M.D., & Bilas, A. (2010). Cloud-based Synchronization of Distributed File System Hierarchies. Cluster Computing Workshops and Posters (CLUSTER WORKSHOPS), 2010 IEEE International Conference on Cluster Computing (Cluster 2010), Crete, Greece, September.
  83. Singh, K., Curtis-Maury, M., McKee, S.A., Blagojevic, F., Nikolopoulos, D.S., & Supinski, B.R.de, Schulz, M. (2010). Comparing scalability prediction strategies on an SMP of CMPs. Proceedings of the 16th international Euro-Par conference on Parallel processing: Part I, Ischia, Italy, (pp. 143-155). Berlin, Heidelberg: Springer-Verlag (3-642-15276-7, 978-3-642-15276-4).
  84. Fountoulakis, M., Marazakis, M., Flouris, M.D., & Bilas, A. (2010). DARC: design and evaluation of an I/O controller for data protection. Proceedings of the 3rd Annual Haifa Experimental Systems Conference(SYSTOR 2010), Haifa, Israel, (pp. 20:1-20:12). New York, NY, USA: ACM (978-1-60558-908-4).
  85. Rafique, M.M., Butt, A.R., & Nikolopoulos, D.S. (2010). Designing Accelerator-Based Distributed Systems for High Performance. Proceedings of the 2010 10th IEEE/ACM International Conference on Cluster, Cloud and Grid Computing, (pp. 165-174). Washington, DC, USA: IEEE Computer Society (978-0-7695-4039-9).
  86. Schneidert, Sc., Andrade, H., Gedik, B., Wu, K.L., & Nikolopoulos, D.S. (2010). Evaluation of streaming aggregation on parallel hardware architectures. Proceedings of the Fourth ACM International Conference on Distributed Event-Based Systems, Cambridge, United Kingdom, July 12-15 (pp. 248-257). New York, NY, USA: ACM (978-1-60558-927-5).
  87. Li, D., Supinski, B.R.de, Schulz, M., Cameron, K.W., & Nikolopoulos, D.S. (2010). Hybrid MPI/OpenMP power-aware computing24th IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2010, Atlanta, Georgia, USA, April 19-23 (pp. 1-12).
  88. Ellen, F., Fatourou, P., Ruppert, E., & van Breugel, F. (2010). Non-blocking binary search trees. Proceeding of the 29th ACM SIGACT-SIGOPS symposium on Principles of distributed computing, Zurich, Switzerland, July (pp. 131-140). New York, NY, USA: ACM (978-1-60558-888-9).
  89. Kavadias, S.G., Katevenis, M.G.H., Zampetakis, M., & Nikolopoulos, D.S. (2010). On-chip communication and synchronization mechanisms with cache-integrated network interfaces. CF '10: Proceedings of the 7th ACM international conference on Computing frontiers, Bertinoro, Italy, (pp. 217-226). New York, NY, USA: ACM (978-1-4503-0044-5).
  90. Li, D., Nikolopoulos, D.S., Cameron, K.W., & Supinski, B.R.de, Schulz, M. (2010). Power-aware MPI task aggregation prediction for high-end computing systems24th IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2010, Atlanta, Georgia, USA, April 19-23 (pp. 1-12). Atlanta, Georgia, USA: IEEE.
  91. Sebepou, Z., & Magoutis, K. (2010). Scalable storage support for data stream processing. In Proceedings of 26th IEEE Conference on Mass Storage Systems and Technologies (MSST 2010): Research Track, Incline Village Lake Tahoe, Nevada, May. Los Alamitos, CA, USA: IEEE Computer Society.
  92. Yeom, J.S., & Nikolopoulos, D.S. (2010). Strider: Runtime Support for Optimizing Strided Data Accesses on Multi-Cores with Explicitly Managed Memories. Proceedings of the 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis, (pp. 1-11). Washington, DC, USA: IEEE Computer Society (978-1-4244-7559-9).
  93. Tzenakis, G., Kapelonis, K., Alvanos, M., Koukos, K., Nikolopoulos, D.S., & Bilas, A. (2010). Tagged Procedure Calls (TPC): Efficient runtime support for task-based parallelism on the cell processor. 5th International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2010, Pisa, 25 January 2010 through 27 January 2010 (vol. 5952 LNCS, pp. 307-321). (03029743; 3642115144 (ISBN); 9783642115141 (ISBN)).
  94. Makatos, A., Klonatos, Y., Marazakis, M., Flouris, M.D., & Bilas, A. (2010). Using transparent compression to improve SSD-based I/O caches. In Proceedings of the 5th European conference on Computer systems (EuroSys '10), Paris, France, April (pp. 1-14). New York, NY, USA: ACM (978-1-60558-577-2).
  95. Makatos, A., Klonatos, Y., Marazakis, M., Flouris, M.D., & Bilas, A. (2010). ZBD: Using Transparent Compression at the Block Level to Increase Storage Space Efficiency. In Proc. of The 6th IEEE International Workshop on Storage Network Architecture and Parallel I/Os (SNAPI 2010), Incline Village, NV, USA, May (pp. 61-70).
  96. Schneider, Sc., Yeom, J.S., Rose, B., Linford, J.C., Sandu, A., & Nikolopoulos, D.S. (2009). A comparison of programming models for multiprocessors with explicitly managed memory hierarchies. Proceedings of the 14th ACM SIGPLAN symposium on Principles and practice of parallel programming, San Jose, CA, USA, (pp. 131-140). ACM New York, NY, USA.
  97. Kyriakoulakos, K., & Pnevmatikatos, D. (2009). A novel SRAM-based FPGA architecture for efficient TMR fault tolerance support. FPL 09: 19th International Conference on Field Programmable Logic and Applications, Prague, 31 August 2009 through 2 September 2009 (pp. 193-198). (9781424438921 (ISBN)).
  98. Yeom, J.S., & Nikolopoulos, D.S. (2009). A Runtime Framework for Optimizing Multi-Dimensional Array Accesses on Multi-core Processors. Proceedings of the First International Workshop on Programming Models for Emerging Architectures (PMEA), held in conjunction with the 18th International Conference on Parallel Architectures and Compilation Techniques (PACT), Raleigh, NC, USA.
  99. Rafique, M.M., Rose, B., Butt, A.R., & Nikolopoulos, D.S. (2009). CellMR: A framework for supporting mapreduce on asymmetric cell-based clusters. IPDPS '09: Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing, Miami, Florida, USA, (pp. 1-12). Washington, DC, USA: IEEE Computer Society (978-1-4244-3751-1).
  100. Afratis, P., Galanakis, C., Sotiriades, E., Mplemenos, G.G., Chrysos, G., Papaefstathiou, I., & Pnevmatikatos, D. (2009). Design and implementation of a database filter for BLAST acceleration. 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09, Nice, 20 April 2009 through 24 April 2009 (pp. 166-171). (15301591; 9783981080155 (ISBN)).
  101. Kontos, D., Papaefstathiou, I., & Pnevmatikatos, D. (2009). Design space exploration of reconfigurable systems for calculating flying object"s optimal noise reduction paths. FPL 09: 19th International Conference on Field Programmable Logic and Applications, Prague, 31 August 2009 through 2 September 2009 (pp. 282-287). (9781424438921 (ISBN)).
  102. Brzezniak, M., Meyer, N., Flouris, M.D., & Bilas, A. (2009). Evaluation of Custom vs Commodity Technology-based Storage Elements. 3rd CoreGRID Workshop on Grid Middleware 2008, (pp. 1-9).
  103. Mangas, E., & Bilas, A. (2009). FLASH: Fine-grained localization in wireless sensor networks using acoustic sound transmissions and high precision clock synchronization. 2009 29th IEEE International Conference on Distributed Computing Systems Workshops, ICDCS, 09, Montreal, QC, 22 June 2009 through 26 June 2009 (pp. 289-298). (9780769536606 (ISBN)).
  104. Kalokairinos, G., Papaefstathiou, V., Nikiforos, G., Kavadias, S.G., Katevenis, M.G.H., Pnevmatikatos, D., & Yang, X. (2009). FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability. 2009 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2009, Samos, 20 July 2009 through 23 July 2009 (pp. 149-156). (9781424445011 (ISBN)).
  105. Panagiotakis, G., Flouris, M.D., & Bilas, A. (2009). Reducing disk I/O performance sensitivity for large numbers of sequential streams. 2009 29th IEEE International Conference on Distributed Computing Systems Workshops, ICDCS, 09, Montreal, QC, 22 June 2009 through 26 June 2009 (pp. 22-31). (9780769536606 (ISBN)).
  106. Blagojevic, F., Iancu, C., Yelick, K.A., Curtis-Maury, M., Nikolopoulos, D.S., & Rose, B. (2009). Scheduling dynamic parallelism on accelerators. Proceedings of the 6th Conference on Computing Frontiers, Ischia, Italy, 18-20 May (pp. 161-170). ACM.
  107. Fatourou, P., & Kallimanis, N. (2009). The RedBlue adaptive universal constructions. DISC '09: Proceedings of the 23rd international conference on Distributed computing, Elche, Spain, (pp. 127-141). Berlin, Heidelberg: Springer-Verlag (3-642-04354-2, 978-3-642-04354-3).
  108. Passas, S., Magoutis, K., & Bilas, A. (2009). Towards 100 gbit/s ethernet: multicore-based parallel communication protocol design. ICS '09: Proceedings of the 23rd international conference on Supercomputing, Yorktown Heights, NY, USA, (pp. 214-224). New York, NY, USA: ACM (978-1-60558-498-0).
  109. Luna, J., Dikaiakos, M., Gjermundrod, H., Flouris, M.D., Marazakis, M., & Bilas, A. (2009). Using gLite to Implement a Secure ICGrid. In CoreGRID Workshop on Grid Middleware 2008, June (pp. 1-15).
  110. Sebepou, Z., Magoutis, K., Marazakis, M., & Bilas, A. (2008). A Comparative Experimental Study of Parallel File Systems for Large-Scale Data Processing. LASCO, Boston, MA, USA, June 23.
  111. Luna, J., Flouris, M.D., Marazakis, M., Bilas, A., Dikaiakos, M., Gjermundrod, H., & Kyprianou, Th. (2008). A Data-Centric Security Analysis Of ICGrid. April 2008 (pp. 197-208).
  112. Nikiforos, G., Kalokairinos, G., Papaefstathiou, V., Kavadias, S.G., Pnevmatikatos, D., & Katevenis, M.G.H. (2008). A run-time Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability. 6th HiPEAC Industrial Workshop, 26 November.
  113. Luna, J., Flouris, M.D., Marazakis, M., Bilas, A., Stagni, F., Forti, A., Ghiselli, A., Magnoni, L., & Zappi, R. (2008). An Analysis of Security Services in Grid Storage Systems. June 25-26 (pp. 171-185). Dresden, Germany.
  114. Brzezniak, M., Meyer, N., Flouris, M.D., Lachaize, R., & Bilas, A. (2008). Analysis of Grid Storage Element Architectures: High-end Fiber-Channel vs. Emerging Cluster-based Networked Storage. (pp. 187-201).
  115. Chrysos, N.I., & Dimitrakopoulos, G. (2008). Backlog-aware crossbar schedulers: A new algorithm and its efficient hardware implementation. 16th Annual IEEE Symposium on High-Performance Interconnects, HOT Interconnects, Stanford, CA, 26 August 2008 through 28 August 2008 (pp. 67-74). (15504794; 9780769533803 (ISBN)).
  116. Aji, A.M., Feng, W.Ch., Blagojevic, F., & Nikolopoulos, D.S. (2008). Cell-SWat: modeling and scheduling wavefront computations on the cell broadband engine. CF '08: Proceedings of the 2008 conference on Computing frontiers, Ischia, Italy, (pp. 13-22). New York, NY, USA: ACM (978-1-60558-077-7).
  117. Luna, J., Dikaiakos, M., Kyprianou, Th., Bilas, A., & Marazakis, M. (2008). Data privacy considerations in Intensive Care Grids. 6th Annual HealthGrid Conference - Global HealthGrid: E-Science Meets Biomedical Informatics, HealthGrid 2008, Chicago, IL, 2 June 2008 through 4 June 2008 (vol. 138, pp. 178-187). (09269630; 9781586038748 (ISBN)).
  118. Passas, S., Kotsis, G., Karlsson, S., & Bilas, A. (2008). Exploiting spatial parallelism in ethernet-based cluster interconnects. 
  119. Dimitrakopoulos, G., Chrysos, N.I., & Galanopoulos, K. (2008). Fast arbiters for on-chip network switches. 26th IEEE International Conference on Computer Design 2008, ICCD, Lake Tahoe, CA, 12 October 2008 through 15 October 2008 (pp. 664-670). (9781424426584 (ISBN)).
  120. Olesinski, W., Eberle, H., Gura, N., & Chrysos, N.I. (2008). Flow control in Output Buffered Switch with Input Groups. In Proceedings of the IEEE High Performance Switching and Routing (HPSR08), Shanghai, China, May 15-17 (pp. 6-12).
  121. Flouris, M.D., Lachaize, R., & Bilas, A. (2008). Orchestra: Extensible Block-Level Support for Resource and Data Sharing in Networked Storage Systems. Parallel and Distributed Systems, 2008. ICPADS '08. 14th IEEE International Conference on, December 2008 (pp. 237-244). (1521-9097).
  122. Luna, J., Flouris, M.D., Marazakis, M., & Bilas, A. (2008). Providing security to the Desktop Data Grid. 
  123. Blagojevic, F., Curtis-Maury, M., Jae-Seung, Y., Schneider, Sc., & Nikolopoulos, D.S. (2008). Scheduling Asymmetric Parallelism on a PlayStation3 Cluster. Cluster Computing and the Grid, 2008. CCGRID '08. 8th IEEE International Symposium on, Lyon, France, May (pp. 146-153).
  124. Katevenis, M.G.H. (2008). Towards unified mechanisms for inter-processor communication. Embedded Computer Systems: Architectures, Modeling, and Simulation, 2008. SAMOS 2008. International Conference on, (pp. iii-iii).
  125. Andrikos, N., Lavagno, L., Pandini, D., & Sotiriou, Ch.P. (2007). A fully-automated desynchronization flow for synchronous circuits. 2007 44th ACM/IEEE Design Automation Conference, DAC '07, San Diego, CA, 4 June 2007 through 8 June 2007 (pp. 982-985). (0738100X; 1595936270 (ISBN); 9781595936271 (ISBN)).
  126. Dimopoulos, V., Papaefstathiou, I., & Pnevmatikatos, D. (2007). A Memory-Efficient Reconfigurable Aho-Corasick FSM Implementation for Intrusion Detection Systems. Proceedings of 2007 International Conference on Embedded Computer Systems: Architectures, Modelling and Simulation (IC-SAMOS 2007), Samos, Greece, 16-19 July (pp. 186-193).
  127. Mihelogiannakis, G., Pnevmatikatos, D., & Katevenis, M.G.H. (2007). Approaching ideal NoC latency with pre-configured routes. NOCS 2007: First International Symposium on Networks-on-Chip, Princeton, NJ, 7 May 2007 through 9 May 2007 (pp. 153-162). (0769527736 (ISBN); 9780769527734 (ISBN)).
  128. Passas, G., & Katevenis, M.G.H. (2007). Asynchronous operation of bufferless crossbars. 2007 IEEE Workshop on High Performance Switching and Routing, HPSR, Brooklyn, NY, 30 May 2007 through 1 June 2007 (pp. 187-192). (1424412064 (ISBN); 9781424412068 (ISBN)).
  129. Chrysos, N.I. (2007). Congestion management for non-blocking clos networks. ANCS '07: Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems, Orlando, Florida, USA, (pp. 117-126). New York, NY, USA: ACM (978-1-59593-945-6).
  130. Chrysos, N.I., & Katevenis, M.G.H. (2007). Crossbars with minimally-sized crosspoint buffers. 2007 IEEE Workshop on High Performance Switching and Routing, HPSR, Brooklyn, NY, 30 May 2007 through 1 June 2007 (pp. 180-186). (1424412064 (ISBN); 9781424412068 (ISBN)).
  131. Papaefstathiou, I., & Papaefstathiou, V. (2007). Memory-Efficient 5D Packet Classification At 40 Gbps. INFOCOM 2007. 26th IEEE International Conference on Computer Communications. IEEE, Anchorage Alaska, USA, 6-12 may (pp. 1370-1378). (0743-166X).
  132. Karlsson, S., Passas, S., Kotsis, G., & Bilas, A. (2007). MultiEdge: An edge-based communication subsystem for scalable commodity servers. 21st International Parallel and Distributed Processing Symposium, IPDPS 2007, Long Beach, CA, 26 March 2007 through 30 March 2007. (1424409101 (ISBN); 9781424409105 (ISBN)).
  133. Marazakis, M., Papaefstathiou, V., & Bilas, A. (2007). Optimization and bottleneck analysis of network block I/O in commodity storage systems. (pp. 33-42).
  134. Papaefstathiou, V., Pnevmatikatos, D., Marazakis, M., Kalokairinos, G., Ioannou, A., Papamichael, M., Kavadias, S.G., Mihelogiannakis, G., & Katevenis, M.G.H. (2007). Prototyping efficient interprocessor communication mechanisms. 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2007, Samos, 16 July 2007 through 19 July 2007 (pp. 26-33). (1424410584 (ISBN); 9781424410583 (ISBN)).
  135. Német, Z., Flouris, M.D., Lachaize, R., & Bilas, A. (2007). Support for Automatic Diagnosis and Dynamic Configuration of Scalable Storage Systems. Dresden, Germany, August 29-September 1 (vol. 4375/2007, pp. 15-21). Springer Berlin / Heidelberg.
  136. Papaefstathiou, V., & Papaefstathiou, I. (2006). A hardware-engine for layer-2 classification in low-storage, ultra-high bandwidth environments. DATE '06: Proceedings of the conference on Design, automation and test in Europe, Munich, Germany, (pp. 112-117). 3001 Leuven, Belgium, Belgium: European Design and Automation Association (3-9810801-0-6).
  137. Kassapaki, E., Mattheakis, P.M., & Sotiriou, Ch.P. (2006). Actual-delay circuits on FPGA: Trading-off LUTs for speed. 2006 International Conference on Field Programmable Logic and Applications, FPL, Madrid, 28 August 2006 through 30 August 2006 (pp. 599-604). (142440312X (ISBN); 9781424403127 (ISBN)).
  138. Papaefstathiou, V., Kalokairinos, G., Ioannou, A., Papamichael, M., Mihelogiannakis, G., Kavadias, S.G., Vlachos, E., Pnevmatikatos, D., & Katevenis, M.G.H. (2006). An FPGA-based Prototyping Platform for Research in High-Speed Interprocessor Communication. In the 2nd HiPEAC Industrial Workshop on Embedded Computing, Eindhoven, Netherlands, 17 October.
  139. Papaefstathiou, I., & Papaefstathiou, V. (2006). An innovative low-cost Classification Scheme for combined multi-Gigabit IP and Ethernet Networks. Proc. IEEE International Conference on Communications (ICC2006), Istanbul, Turkey, 11-15 June.
  140. Marazakis, M., Xinidis, K., Papaefstathiou, V., & Bilas, A. (2006). Efficient remote block-level I/O over an RDMA-capable NIC. 20th Annual International Conference on Supercomputing, ICS 2006, Cairns, Queensland, 28 June 2006 through 1 July 2006 (pp. 97-106). (1595932828 (ISBN); 9781595932822 (ISBN)).
  141. Marazakis, M., Papaefstathiou, V., Kalokairinos, G., & Bilas, A. (2006). Experiences from debugging a PCIX-based RDMA-capable NIC. 2006 IEEE International Conference on Cluster Computing, Cluster 2006, Barcelona, 25 September 2006 through 28 September 2006. (15525244; 1424403286 (ISBN); 9781424403288 (ISBN)).
  142. Christodoulopoulou, R., Manassiev, K., Bilas, A., & Amza, C. (2006). Fast and transparent recovery for continuous availability of cluster-based servers. 2006 ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP '06, New York, NY, 29 March 2006 through 31 March 2006 (vol. 2006, pp. 221-229). (1595931899 (ISBN); 9781595931894 (ISBN)).
  143. Passas, G., & Katevenis, M.G.H. (2006). Packet mode scheduling in buffered crossbar (CICQ) switches. 2006 Workshop on High Performance Switching and Routing, HPSR 2006, Poznan, 7 June 2006 through 9 June 2006 (pp. 105-112). (0780395697 (ISBN); 9780780395695 (ISBN)).
  144. Sourdis, I., Dimopoulos, V., Pnevmatikatos, D., & Vassiliadis, S. (2006). Packet pre-filtering for network intrusion detection. 2nd ACM/IEEE Symposium on Architectures for Networking and Communications Systems, ANCS 2006, San Jose, CA, 3 December 2006 through 5 December 2006 (pp. 183-192). (1595935800 (ISBN); 9781595935809 (ISBN)).
  145. Chrysos, N.I., & Katevenis, M.G.H. (2006). Preventing buffer-credit accumulations in switches with small, shared output queuesProc. IEEE Workshop on High Performance Switching and Routing (HPSR 2006), Poznan, Poland, 7-9 June (pp. 8 pp.).
  146. Martinez, A., Apostolopoulos, G., Alfaro, F.J., Sanchez, J.L., & Duato, J. (2006). QoS support for video transmission in high-speed interconnects. 2nd International Conference on High Performance Computing and Communications, HPCC 2006, Munich, 13 September 2006 through 15 September 2006 (vol. 4208 LNCS, pp. 631-641). (03029743; 3540393684 (ISBN); 9783540393689 (ISBN)).
  147. Chrysos, N.I., & Katevenis, M.G.H. (2006). Scheduling in non-blocking buffered three-stage switching fabrics. INFOCOM 2006: 25th IEEE International Conference on Computer Communications, Barcelona, 23 April 2006 through 29 April 2006. (0743166X; 1424402212 (ISBN); 9781424402212 (ISBN)).
  148. Flouris, M.D., Lachaize, R., & Bilas, A. (2006). Using lightweight transactions and snapshots for fault-tolerant services based on shared storage bricks. 2006 IEEE International Conference on Cluster Computing, Cluster 2006, Barcelona, 25 September 2006 through 28 September 2006. (15525244; 1424403286 (ISBN); 9781424403288 (ISBN)).
  149. Apostolopoulos, G., & Hassapis, C. (2006). V-eM: A Cluster of Virtual Machines for Robust, Detailed, and High-Performance Network Emulation. Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, 2006. MASCOTS 2006. 14th IEEE International Symposium on, California, USA, September 11 -13 (pp. 117-126). (1526-7539).
  150. Pnevmatikatos, D., & Arelakis, A. (2006). Variable-length hashing for exact pattern matching. 2006 International Conference on Field Programmable Logic and Applications, FPL, Madrid, 28 August 2006 through 30 August 2006 (pp. 405-410). (142440312X (ISBN); 9781424403127 (ISBN)).
  151. Papaefstathiou, V., & Papaefstathiou, I. (2005). A low-cost MAC Classification Engine. Proc. 10th Panhellenic Conference on Informatics, (PCI2005), Volos, Greece, 11-13 November.
  152. Papaefstathiou, V., & Papaefstathiou, I. (2005). A Memory Efficient, 100 Gb/sec MAC Classification Engine. LCN '05: Proceedings of the The IEEE Conference on Local Computer Networks 30th Anniversary, (pp. 470-471). Washington, DC, USA: IEEE Computer Society (0-7695-2421-4).
  153. Sourdis, I., Pnevmatikatos, D., Wang, S., & Vassiliadis, S. (2005). A reconfigurable perfect-hashing scheme for packet inspection. 2005 International Conference on Field Programmable Logic and Applications, FPL, Tampere, 24 August 2005 through 26 August 2005 (vol. 2005, pp. 644-647). (0780393627 (ISBN); 9780780393622 (ISBN)).
  154. Flourish, M.D., Anastasiadis, S.V., & Bilas, A. (2005). Block-level virtualization: How far can we go?. Local to Global Data Interoperability - Challenges and Technologies, 2005, Sardinia, 20 June 2005 through 24 June 2005 (vol. 2005, pp. 98-102). (0780392280 (ISBN); 9780780392281 (ISBN)).
  155. Zebilis, V., & Sotiriou, Ch.P. (2005). Controlling event spacing in self-timed ringsIn Proceedings of the 11th IEEE International Conference on Asynchronous Circuits and Systems (ASYNC), New York, USA, 14-16 March (pp. 109). (1522-8681).
  156. Yannakopoulos, J., & Bilas, A. (2005). CORMOS: A communication-oriented runtime system for sensor networks. 2nd European Workshop onWireless Sensor Networks, EWSN 2005, Istanbul, 31 January 2005 through 2 February 2005 (vol. 2005, pp. 342-353).
  157. Papadopoulos, G., & Pnevmatikatos, D. (2005). Hashing + Memory = low cost, exact pattern matching. 2005 International Conference on Field Programmable Logic and Applications, FPL, Tampere, 24 August 2005 through 26 August 2005 (vol. 2005, pp. 39-44). (0780393627 (ISBN); 9780780393622 (ISBN)).
  158. Dimopoulos, V., Papadopoulos, G., & Pnevmatikatos, D. (2005). On the importance of header classification in HW/SW network intrusion detection systems. 10th Panhellenic Conference on Informatics, PCI 2005, Volos, Greece, 11 November 2005 through 13 November 2005 (vol. 3746 LNCS, pp. 661-671). (03029743; 3540296735 (ISBN); 9783540296737 (ISBN)).
  159. Xinidis, D., Bilas, A., & Flouris, M.D. (2005). Performance evaluation of commodity iSCSI-based storage systems. Twenty-second IEEE/Thirteenth NASA Goddard Conference on Mass Storage Systems and Technologies, IEEE/NASA MSST2005, Monterey, CA, 11 April 2005 through 14 April 2005 (pp. 261-269). (0769523188 (ISBN)).
  160. Chrysos, N.I., & Katevenis, M.G.H. (2005). Scheduling in switches with small internal buffers. GLOBECOM '05: IEEE Global Telecommunications Conference, 2005, St. Louis, MO, 28 November 2005 through 2 December 2005 (vol. 1, pp. 614-619). (0780394143 (ISBN); 9780780394148 (ISBN)).
  161. Katevenis, M.G.H., & Passas, G. (2005). Variable-size multipacket segments in buffered crossbar (CICQ) architectures. 2005 IEEE International Conference on Communications, ICC 2005, Seoul, 16 May 2005 through 20 May 2005 (vol. 2, pp. 999-1004). (05361486).
  162. Flouris, M.D., & Bilas, A. (2005). Violin: A Framework for Extensible Block-Level Storage. MSST '05: Proceedings of the 22nd IEEE / 13th NASA Goddard Conference on Mass Storage Systems and Technologies, Monterey, CA, USA, (pp. 128-142). Washington, DC, USA: IEEE Computer Society (0-7695-2318-8).
  163. Xinidis, D., Flouris, M.D., & Bilas, A. (2005). Virtual timers: Using hardware physical timers for profiling kernel code-paths. In Proc. of 8th Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-8), February.
  164. Efthymiou, A., Sotiriou, Ch.P., & Edwards, D. (2004). Automatic scan insertion and pattern generation for asynchronous circuits. Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04, Paris, 16 February 2004 through 20 February 2004 (vol. 1, pp. 672-673). (0769520855 (ISBN)).
  165. Flouris, M.D., & Bilas, A. (2004). Clotho: Transparent data versioning at the block i/o level. In 12th NASA Goddard & 21st IEEE Conference on Mass Storage Systems and Technologies (MSST2004), April.
  166. Cortadella, J., Kondratyev, A., Lavagno, L., & Sotiriou, Ch.P. (2004). Coping with the variability of combinational logic delays. Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on, San Jose, USA, October (pp. 505-508). (1063-6404).
  167. Cortadella, J., Kondratyev, A., Lavagno, L., Lwin, K., & Sotiriou, Ch.P. (2004). From synchronous to asynchronous: An automatic approach. Proceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 04, Paris, 16 February 2004 through 20 February 2004 (vol. 2, pp. 1368-1369). (0769520855 (ISBN)).
  168. Antonatos, S., Anagnostakis, K.G., & Markatos, E.P. (2004). Generating realistic workloads for network intrusion detection systems. Proceedings of the Fourth International Workshop on Software and Performance, WOSP '04, Redwood Shores, CA, 14 January 2004 through 16 January 2004 (pp. 207-215). (1581136730 (ISBN)).
  169. Cavanna, C.D., Abdelrahman, T.S., Bilas, A., & Jamieson, P. (2004). Jupiter/SVM: A JVM-based single system image for clusters of workstations. Proceedings of the 16th IASTED International Conference on Parallel and Distributed Computing and Systems, Cambridge, MA, 9 November 2004 through 11 November 2004 (vol. 16, pp. 121-129). (10272658).
  170. Chrysos, N.I., & Katevenis, M.G.H. (2004). Multiple priorities in a two-lane buffered crossbar. GLOBECOM '04 - IEEE Global Telecommunications Conference, Dallas, TX, 29 November 2004 through 3 December 2004 (vol. 2, pp. 1180-1186).
  171. Georgakopoulos, G.F. (2004). Nash equilibria as a fundamental issue concerning network-switches design. In Proceedings of the IEEE International Conference on Communications (ICC 2004), June (vol. 2, pp. 1080-1084).
  172. Abdelkhalek, A., & Bilas, A. (2004). Parallelization and performance of interactive multiplayer game servers. Proceedings - 18th International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM), Santa Fe, NM, 26 April 2004 through 30 April 2004 (vol. 18, pp. 1017-1026). (0769521320 (ISBN); 9780769521329 (ISBN)).
  173. Antonatos, S., Anagnostakis, K.G., Markatos, E.P., & Polychronakis, M. (2004). Performance analysis of content matching intrusion detection systems. Proceedings - 2004 International Symposium on Applications and the Internet (Saint 2004), Tokyo, 26 January 2004 through 30 January 2004 (pp. 208-215). (0769520685 (ISBN)).
  174. Sourdis, I., & Pnevmatikatos, D. (2004). Pre-decoded CAMs for efficient and high-speed NIDS pattern matching. Proceedings - 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2004, Napa, CA, 20 April 2004 through 23 April 2004 (pp. 258-267). (0769522300 (ISBN)).
  175. Katevenis, M.G.H., Passas, G., Simos, D.G., Papaefstathiou, I., & Chrysos, N.I. (2004). Variable packet size buffered crossbar (CICQ) switches. 2004 IEEE International Conference on Communications, Paris, 20 June 2004 through 24 June 2004 (vol. 2, pp. 1090-1096). (05361486).
  176. Cortadella, J., Kondratyev, A., Lavagno, L., & Sotiriou, Ch.P. (2003). A Concurrent Model for De-SynchronizationIn Proceedings of the 12th International Workshop on Logic and Synthesis (IWLS), May.
  177. Sotiriou, Ch.P., & Papaefstathiou, I. (2003). A Design-Space Exploration of Alternative DES Implementations.  In Proceedings of 10th IEEE International Conference on Electronics, Circuits and Systems, (ICECS2003), United Arab Emirates, December 14 - 17. (0141-9331).
  178. Charitakis, I., Anagnostakis, K.G., & Markatos, E.P. (2003). An Active Traffic Splitter Architecture for Intrusion DetectionMASCOTS, (pp. 238-241). IEEE Computer Society (0-7695-2039-1).
  179. Amde, M., Blunno, I., & Sotiriou, Ch.P. (2003). Automating the design of an asynchronous DLX microprocessor. Proceedings of the 40th Design Automation Conference, Anaheim, CA, 2 June 2003 through 6 June 2003 (pp. 502-507). (0738100X).
  180. Sapountzis, G., & Katevenis, M.G.H. (2003). Benes Switching Fabrics with O(N)-Complexity Internal Backpressure. Proc. IEEE Workshop on High Performance Switching and Routing (HPSR 2003), tORINO, iTALY, June (pp. 11-16).
  181. Charitakis, I., Pnevmatikatos, D., Markatos, E.P., & Anagnostakis, K.G. (2003). Code generation for packet header intrusion analysis on the IXP1200 network processor. Vienna, Austria, September 24-26 (vol. 2826, pp. 226-239). (03029743).
  182. Sotiriou, Ch.P., & Lavagno, L. (2003). De-synchronization: asynchronous circuits from synchronous specificationsSOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip] title={De-synchronization: asynchronous circuits from synchronous specifications, Portland, Oregon, 17-20 September (pp. 165).
  183. Sotiriou, Ch.P., & Papaefstathiou, I. (2003). Design-space exploration of a cryptography algorithm. In Proceedings of the the 10th IEEE International Conference on Electronics, Circuits and Systems (ICECS), United Arab Emirates, December 2003 (vol. 2, pp. 858-861 Vol.2).
  184. Anagnostakis, K.G., Antonatos, S., Markatos, E.P., & Polychronakis, M. (2003). E2XB: : A Domain-Specific String Matching Algorithm for Intrusion Detection. SEC; Security and Privacy in the Age of Uncertainty, {IFIP} {TC11} 18$^th$ International Conference on Information Security ({SEC2003}), May 26-28, 2003, Athens, Greece; IFIP Conference Proceedings,, (vol. 250, pp. 217-228). Kluwer (1-4020-7449-2).
  185. Sourdis, I., & Pnevmatikatos, D. (2003). Fast, large-scale string match for a 10Gbps FPGA-based network intrusion detection system. Lisbon, Portugal, September 1-3 (vol. 2778, pp. 880-889). (03029743).
  186. Charitakis, I., Pnevmatikatos, D., Markatos, E.P., & Anagnostakis, K.G. (2003). S2I: a Tool for Automatic Rule Match Compilation for the IXP Network Processor. In Proceedings of the 7th International Workshop on Software and Compilers for Embedded Systems (SCOPES 2003), Vienna, Austria, 24-26 September.
  187. Coppens, J., Van den Berghe, S., Bos, H., Markatos, E.P., De Turck, F., Øslebø, A., & Ubik, S. (2003). SCAMPI: A scalable and programmable architecture for monitoring gigabit networks. Workshop on End-to-End Monitoring Techniques and Services (E2EMON), Belfast, Ireland, September 7-10 (vol. 2839, pp. 475-487). (03029743).
  188. Chrysos, N.I., & Katevenis, M.G.H. (2003). Weighted fairness in buffered crossbar schedulingProc. IEEE Workshop on High Performance Switching and Routing (HPSR 2003), Torino, Italy, June (pp. 17-22).
  189. Markatos, E.P., Antonatos, S., Polychronakis, M., & Anagnostakis, K.G. (2002). Exclusion-based signature matching for intrusion detection. In Proceedings of the IASTED International Conference on Communications and Computer Networks (CCN, (pp. 146-152). ACTA Press.
  190. Sotiriou, Ch.P. (2002). Implementing asynchronous circuits using a conventional EDA tool-flow. In Proceedings of the 39th Design Automation Conference (DAC), June (pp. 415-418). (0738-100X).
  191. Papaefstathiou, I., & Sotiriou, Ch.P. (2002). Read, use, simulate, experiment and build: an integrated approach for teaching computer architecture. WCAE '02: Proceedings of the 2002 workshop on Computer architecture education (in conjunction to the 29th International Symposium on Computer Architecture), Anchorage, Alaska, May (pp. 20). New York, NY, USA: ACM.
  192. Markatos, E.P. (2002). Speeding up TCP/IP: Faster processors are not enough. 21st IEEE International Performance, Computing, and Communications Conference, Phoenix, AZ, 3 April 2002 through 5 April 2002 (pp. 341-345).
  193. Markatos, E.P. (2002). Tracing a Large-Scale Peer to Peer System: An Hour in the Life of GnutellaCCGRID, (pp. 65-74). IEEE Computer Society (0-7695-1582-7).
  194. Dollas, A., Pnevmatikatos, D., Aslanides, N., Kavadias, S.G., Sotiriades, E., Zogopoulos, S., Papademetriou, K., Chrysos, N.I., Harteros, K., Antonidakis, E., & Petrakis, N. (2001). Architecture and Application of PLATO, A Reconfigurable Active Network Platform. Field-Programmable Custom Computing Machines, 2001. FCCM '01. The 9th Annual IEEE Symposium on, Rohnert Park, CA, April 30 - May 2 (pp. 101-110).
  195. Sotiriou, Ch.P. (2001). Direct-mapped asynchronous finite-state machines in CMOS technology. ASIC/SOC Conference, 2001. In Proceedings of the 14th International ASIC/SOC Conference, Arlington, VA, USA, September (pp. 105-109).
  196. Gialama, E.M., Markatos, E.P., Sevaslidou, J.E., Serpanos, D.N., Kotsovinos, E.N., & Asimakopoulou, X.A. (2001). DIVISOR: Distributed video server for streaming. In Proceedings of the 5th IEEE/WSES International Conference on Circuits, Systems, Communications and Computers (CSCC 2001), July (pp. 4531-4536).
  197. Nikologiannis, A.A., & Katevenis, M.G.H. (2001). Efficient per-flow queueing in DRAM at OC-192 line rate using out-of-order execution techniques. International Conference on Communications (ICC2001), Helsinki, 11 June 2000 through 14 June 2000 (vol. 7, pp. 2048-2052). (05361486).
  198. Markatos, E.P. (2001). On caching search engine query results. 5th International Web Caching and Content Delivery Workshop, 2/1 (vol. 24, pp. 137-143). (0140-3664).
  199. Tziouvaras, Ch.I., & Sartzetakis, S. (2001). Optimizing resource allocation in multi-class IP MPLS DWDM networks. In Proc. of 8th International Conference on Advances in Communications and Control (COMCON), Crete, Greece, 25-29 June.
  200. Ioannou, A., & Katevenis, M.G.H. (2001). Pipelined heap (priority queue) management for advanced scheduling in high-speed networks. International Conference on Communications (ICC2001), Helsinki, 11 June 2000 through 14 June 2000 (vol. 7, pp. 2043-2047). (05361486).
  201. Dollas, A., Pnevmatikatos, D., Aslanides, N., Kavadias, S.G., Sotiriades, E., & Papademetriou, K. (2001). Rapid prototyping of a reusable 4×4 active ATM switch core with the PCI pamette. 12th IEEE International Workshop on Rapid System Prototyping, Monterrey, CA, 25 June 2001 through 27 June 2001 (pp. 17-23). (10746005).
  202. Pnevmatikatos, D., & Kornaros, G. (1999). ATLAS II: Optimizing a 10Gbps single-chip ATM switch. 12th Annual 1999 IEEE International ASIC/SOC Conference, Washington, DC, USA, September 15-18.
  203. Kornaros, G., Pnevmatikatos, D., Mavroidis, D., Vatsolaki, P., Kalokairinos, G., Xanthaki, Ch., Dimitriadis, G., Serpanos, D.N., & Katevenis, M.G.H. (1999). On Optimizing ATLAS I, A 10 Gbps ATM Switch. In the Proceedings of the 7-th Hellenic Conference on Informatics, Ioannina, Greece, August 26-29 (vol. IV, pp. 50-60).
  204. Markatos, E.P., Katevenis, M.G.H., Pnevmatikatos, D., & Flouris, M.D. (1999). Secondary Storage Management for Web Proxies. USENIX Symposium on Internet Technologies and Systems.
  205. Serpanos, D.N., & Wolf, W.H. (1998). Caching Web objects using Zipf"s law. October 5, 1998 (vol. 3527, pp. 320-326). SPIE.
  206. Katevenis, M.G.H., Serpanos, D.N., & Spyridakis, E. (1998). Credit-flow-controlled ATM for MP interconnection: The ATLAS I single-chip ATM switch. Proceedings of the 1998 4th International Symposium on High-Performance Computer Architecture, HPCA, Las Vegas, NV, USA, 31 January 1998 through 4 February 1998 (pp. 47-56). Los Alamitos, CA, United States: Institute of Electrical and Electronics Engineers Computer Society.
  207. Markatos, E.P., Tziviskou, Ch., & Papathanasiou, A E. (1998). Effective Resource Discovery on the World Wide Web. 
  208. Kornaros, G., Pnevmatikatos, D., Vatsolaki, P., Kalokairinos, G., Xanthaki, Ch., Mavroidis, D., Serpanos, D.N., & Katevenis, M.G.H. (1998). Implementation of ATLAS I: a Single-Chip ATM Switch with Backpressure. Proc. IEEE Hot Interconnects 6 Symposium, Stanford, California, USA(pp. 85-96).
  209. Papathanasiou, A E., & Markatos, E.P. (1998). Lightweight transactions on networks of workstations. Proceedings of the 1998 18th International Conference on Distributed Computing Systems, Amsterdam, Neth, 26 May 1998 through 29 May 1998 (pp. 544-551). Piscataway, NJ, United States: IEEE.
  210. Pnevmatikatos, D., Kornaros, G., Kalokairinos, G., & Xanthaki, Ch. (1998). Memory structures of ATLAS I, a high performance, 16×16 ATM switch supporting backpressure. Proceedings of the 1998 11th Annual IEEE International ASIC Conference, Rochester, NY, USA, 13 September 1998 through 16 September 1998 (pp. 23-27). Piscataway, NJ, United States: IEEE (10630988).
  211. Ioannidis, S., Markatos, E.P., & Sevaslidou, J.E. (1998). On Using Network Memory to Improve the Performance of Transaction-Based Systems. In International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA '98).
  212. Papadakakis, N., Markatos, E.P., & Papathanasiou, A E. (1998). Palantir: AVisualization Tool for the World Wide Web. In Proceedings of INET '98 (The Internet Summit), Geneva, Switzerland, July.
  213. Papathanasiou, A E., Markatos, E.P., & Papadakis, S.A. (1998). PaperFinder: A Tool for Scalable Search of Digital Libraries. WebNet; Proceedings of WebNet 98 - World Conference on the {WWW} and Internet & Intranet, Orlando, Florida, {USA November 7-12, 1998, AACE (1-880094-31-2,).
  214. Pnevmatikatos, D., Kornaros, G., Kalokairinos, G., & Xanthaki, Ch. (1998). The Memory Structures of ATLAS I, a High Performance, 16x16 ATM Switch Supporting Backpressure. In Proceedings of the 11th Annual IEEE International ASIC Conference, Rochester, NY, USA, September 13-16 (pp. 23-27).
  215. Markatos, E.P., Katevenis, M.G.H., & Vatsolaki, P. (1998). The Remote Enqueue Operation on Networks of Workstations. CANPC, Las Vegas, Nevada, USA, January 31 - February 1 (pp. 1-14).
  216. Katevenis, M.G.H., Vatsolaki, P., Serpanos, D.N., & Markatos, E.P. (1997). ATLAS: A Single-Chip ATM Switch for NOWs. CANPC, San Antonio, Texas, USA, February 1-2 (pp. 88-101).
  217. Katevenis, M.G.H. (1997). Buffer Requirements of Credit-Based Flow Control when a Minimum Draining Rate is Guaranteed. Proceedings of HPCS '97 (4th IEEE Workshop on Arch. & Impl. of High Perf. Commun. Subsystems), Chalkidiki, Greece, June.
  218. Katevenis, M.G.H., Serpanos, D.N., & Markatos, E.P. (1997). Multi-queue management and scheduling for improved QoS in communication networks. In Proceedings of the European Multimedia Microprocessor Systems and Electronic Commerce (EMMSEC '97, (pp. 906-913).
  219. Kornaros, G., Kozyrakis, Ch., Vatsolaki, P., & Katevenis, M.G.H. (1997). Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow Control. Proceedings of ARVLSI '97 (17th Conference on Advanced Research in VLSI), MI,USA, (pp. 127-144). IEEE Computer Soc. Press (0-8186-7913-1).
  220. Katevenis, M.G.H., Serpanos, D.N., & Spyridakis, E. (1997). Switching fabrics with internal backpressure using the ATLAS I single-chip ATM switch. Proceedings of the 1997 IEEE Global Telecommunications Mini-Conference, Phoenix, AZ, USA, 3 November 1997 through 8 November 1997 (vol. 1, pp. 242-246). Piscataway, NJ, United States: IEEE.
  221. Markatos, E.P., & Katevenis, M.G.H. (1997). User-level DMA without operating system kernel modification. Proceedings of the 1997 3rd International Symposium on High-Performance Computer Architecture, HPCA, San Antonio, TX, USA, 1 February 1997 through 5 February 1997 (pp. 322-331). Los Alamitos, CA, United States: IEEE.
  222. Katevenis, M.G.H., Serpanos, D.N., & Vatsolaki, P. (1996). ATLAS I: A general-purpose, single-chip ATM switch with credit-based flow control. Proceedings of the Hot Interconnects IV Symposium, Stanford Univ., CA, USA, August (pp. 63-73).
  223. Katevenis, M.G.H., & Vatsolaki, P. (1996). ATLAS I: A Single-Chip ATM Switch with HIC Links and Multi-Lane Back-Pressure. EMSYS 96 Conference (ESPRIT OMI 6th Annual Conference: Embedded Microprocessor Systems), Berlin, Germany, September (pp. 126-136). IOS Press (90-5199-300-5).
  224. Markatos, E.P., & Dramitinos, G. (1996). Implementation of a Reliable Remote Memory Pager. USENIX Annual Technical Conference, (pp. 177-190,).
  225. Markatos, E.P. (1996). Issues in reliable network memory paging. Proceedings of the 1996 4th International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, San Jose, CA, USA, 1 February 1996 through 3 February 1996 (pp. 207-211). Piscataway, NJ, United States: IEEE.
  226. Markatos, E.P., & Katevenis, M.G.H. (1996). Telegraphos: high-performance networking for parallel processing on workstation clusters. Proceedings of the 1996 2nd International Symposium on High-Performance Computer Architecture, HPCA, San Jose, CA, USA, 3 February 1996 through 7 February 1996 (pp. 144-153). Los Alamitos, CA, United States: IEEE.
  227. Markatos, E.P. (1996). Using remote memory to avoid disk thrashing: a simulation study. Proceedings of the 1996 4th International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, San Jose, CA, USA, 1 February 1996 through 3 February 1996 (pp. 61-73). Piscataway, NJ, United States: IEEE.
  228. Markatos, E.P., & Dramitinos, G. (1995). Adding flexibility to a remote memory pager. Proceedings of the 4th International Workshop on Object Orientation in Operating Systems, Lund, Swed, 14 August 1995 through 15 August 1995 (pp. 183-186). Los Alamitos, CA, United States: IEEE (10635351).
  229. Markatos, E.P., Katevenis, M.G.H., Kalokairinos, G., & Serpanos, D.N. (1995). An Efficient Processor-Network Interface for Local Area MultiprocessorsProceedings of the 4th Int. Workshop on SCI-based High-Performance Low-Cost Computing, Crete, Greece, 3 October.
  230. Katevenis, M.G.H., Vatsolaki, P., & Efthymiou, A. (1995). Pipelined Memory Shared Buffer for VLSI Switches. SIGCOMM, (pp. 39-48).
  231. Vatsolaki, P., Kalokairinos, G., Stratakis, M., Xanthaki, Ch., Ligerakis, M., Kornaros, G., Dollas, A., Papadourakis, G.M., & Katevenis, M.G.H. (1995). The Implementation of Telegraphos: a High Speed Communication Architecture. In Proceedings of the 5th Panhellenic Informatics Conference, Athens Greece, December.
  232. Katevenis, M.G.H., Vatsolaki, P., Efthymiou, A., & Stratakis, M. (1995). VC-level Flow Control and Shared Buffering in the Telegraphos Switch. Proceedings of the Hot Interconnects III Symposium, Stanford, California, USA, August 10-12.
  233. Ferreira, A., & Grammatikakis, M.D. (1994). Improved probabilistic routing on generalized hypercubes. In Proceedings 6th International PARLE Conference, Athens, Greece, July 4–8 (pp. 1-12).
  234. Markatos, E.P., & Chronaki, C. (1994). Using reference counters in update based coherent memory. 6th International PARLE Conference , Proceedings, Athens, Greece, July 4–8 (pp. 805-808).
  235. Grammatikakis, M.D., Hsu, D., & Hwang, F. (1993). Adaptive and oblivious algorithms for d-cube permutation routing. In Proceedings 4th International Symposium, ISAAC '93, Hong Kong, December 15–17 (pp. 167-175).
  236. Grammatikakis, M.D., & Jwo, J.S. (1993). Simulating Store-Forward Communication.PARCO, (pp. 681-684). Elsevier (0-444-81841-3).
  237. Katevenis, M.G.H., & Tzartzanis, N (1991). Reducing the branch penalty by rearranging instructions in a double-width memory. 4th International Conference on Architectural Support for Programming Languages and Operating Systems, Santa Clara, CA, USA, 8 April 1991 through 11 April 1991 (vol. 26, pp. 15-27). New York, NY, United States: Publ by ACM.
  238. Katevenis, M.G.H., & Blatt, M.G. (1986). SWITCH DESIGN FOR SOFT-CONFIGURABLE WSI SYSTEMS. (pp. 255-270).
  239. Katevenis, M.G.H., & Blatt, M.G. (1985). SWITCH DESIGN FOR SOFT-CONFIGURABLE WSI SYSTEMS. (pp. 197-219).
    Papers in Proceedings (abstract reviewed)

  1. Tzenakis, G., Papatriantafyllou, A., Kesapides, J., Pratikakis , P., Vandierendonck, H., & Nikolopoulos, D.S. (2012). BDDT:: block-level dynamic dependence analysisfor deterministic task-based parallelism. Proceedings of the 17th ACM SIGPLAN symposium on Principles and Practice of Parallel Programming, PPoPP '12, New Orleans, Louisiana, USA, February 25-29 (pp. 301-302). New York, NY, USA: ACM (978-1-4503-1160-1).
  2. Zakkak, F. S., Chasapis , D., Pratikakis , P., Bilas, A., & Nikolopoulos, D.S. (2012). Inference and declaration of independence: Impact on deterministic task parallelism. Proceedings of the 21st international conference on Parallel architectures and compilation techniques (PACT 2012), September 19-23 (pp. 453-454). Minneapolis.
    Poster presentations (abstract reviewed)

  1. Rousopoulos, Ch. , Karandeinos Ektoras, E., Chrysos , G., Dollas, A., & Pnevmatikatos, D. (2017). A Generic High Throughput Architecture for Stream Processing. 26th International Conference on Field Programmable Logic and Applications (FPL 2017), Ghent, Belgium, 4 - 8 September .
  2. Theodoropoulos, D., Alachiotis , N., & Pnevmatikatos, D. (2017). Multi-FPGA Evaluation Platform for Disaggregated ComputingIEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa, CA, USA, 30 April-2 May (pp. 193). IEEE.
  3. Alachiotis , N., Theodoropoulos, D., & Pnevmatikatos, D. (2017). Versatile Deployment of FPGA Accelerators in Disaggregated Data Centers: a Bioinformatics Case Study26th International Conference on Field Programmable Logic and Applications (FPL 2017) , Ghent, Belgium, 4 - 8 September .
  4. Mavridis, S., Pavlidakis, M., Kozanitis, Ch., Chrysos, N., Stamoulias, I., Kachris, C., Soudris, D., & Bilas, A. (2017). VineTalk: Simplifying Software Access and Sharing of FPGAs in Datacenters. 26th International Conference on Field Programmable Logic and Applications (FPL 2017), Ghent, Belgium, 4 - 8 September.
  5. Psathakis, A., Papaefstathiou, V., Katevenis, M.G.H., & Pnevmatikatos, D. (2014). Design Trade-offs in Energy Efficient NoC Architectures8th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2014), Ferrara, Italy, 17-19 September (pp. 186-187).
  6. Ciobanu, C.B., Pnevmatikatos, D., Papadimitriou, K., & Gaydadjiev, G.N. (2013). FASTER run-time reconfiguration management. ICS '13 Proceedings of the 27th international ACM conference on International conference on supercomputing, (pp. 463-464).
  7. Fatourou, P., Iaremko, M., Kosmas, E., & Papadakis, G.E. (2012). Reducing contention in STM4th Workshop on the Theory of Transactional Memory (TransForm/EuroTM WTTM 2012), Madeira, July 2012.
  8. Chrysos, N.I., Chen, L.Y., Minkenberg, C., Kachris, C., & Katevenis, M.G.H. (2010). End-to-end congestion management for non-blocking multi-stage switching fabricsProceedings of the 2010 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, ANCS '10 , San Diego, California, USA, October 25-26.
  9. Fountoulakis, M., Marazakis, M., Flouris, M.D., & Bilas, A. (2010). A high performance commodity I/O controller for storage virtualization. Poster in the ACM/SIGOPS European Conference on Computer Systems (EuroSys 2010), Paris, France, April. New York, NY, USA: ACM.
  10. Kachris, C., Nikiforos, G., Papaefstathiou, V., Yang, X., Kavadias, S.G., & Katevenis, M.G.H. (2010). Low-latency Explicit Communication and Synchronization in Scalable Multi-core Clusters. Cluster Computing Workshops and Posters (CLUSTER WORKSHOPS), IEEE International Conference on Cluster Computing (CLUSTER 2010), September 20-24.
      Invited papers

    1. Papadimitriou, K., Vatsolakis, C., & Pnevmatikatos, D. (2012). Acceleration of computationally-intensive kernels in the reconfigurable eraReCoSoC : 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, (pp. 1-5).
    2. Tzenakis, G., Kapelonis, K., Alvanos, M., Koukos, K., Nikolopoulos, D.S., & Bilas, A. (2010). Tagged Procedure Calls (TPC): Efficient runtime support for task-based parallelism on the cell processor. 5th International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2010, Pisa, January 25-27 (vol. 5952 LNCS, pp. 307-321). (03029743, 3642115144 (ISBN), 9783642115141 (ISBN)).
        Tutorials

      1. Marazakis, M., Flouris, M.D., & Bilas, A. (2010). Storage Virtualization and High-Performance I/O: Storage I/O Stack Design and Implementation. Tutorial in the ACM/SIGOPS European Conference on Computer Systems, Paris, France, April (pp. 1-14). New York, NY, USA: ACM.
        Edited Proceedings

      1. Fatourou, P., Jiménez, E., & Pedone, F. (2016). 20th International Conference on Principles of Distributed Systems (OPODIS'2016). Madrid, Spain, 13-16 December 2016, Madrid, Spain. (978-3-95977-031-6).
      2. Katevenis, M.G.H., Martonosi, M., Kozyrakis, Ch., Temam, O., & Ungerer, Th. (2011). Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers (HiPEAC'11), ACM Digital Library. Heraklion, Crete, Greece, 24-26 January (223 pages). (978-1-4503-0241-8).
      3. Gritzalis, S., Plexousakis, D., & Pnevmatikatos, D. (2009). PCI 2009, 13th Panhellenic Conference on Informatics, 10-12 September 2009, Corfu, Greece. Panhellenic Conference on Informatics, IEEE Computer Society (978-0-7695-3788-7).

      WorkShops (15)

        Papers in Proceedings (full-paper reviewed)

      1. Papagiannis, A., Saloustros, G., Marazakis, M., & Bilas, A. (2016). User-Space I/O for μs-level Storage DevicesHigh Performance Computing, ISC High Performance 2016 International Workshops ExaComm, E-MuCoCoS, HPC-IODC, IXPUG, IWOPH, P3MA, VHPC, WOPSSS , Frankfurt, Germany, (vol. 9945 LNCS, pp. 638-648). Springer.
      2. Gonzalez-Ferez, P., & Bilas, A. (2015). NUMA impact on network storage protocolsover high-speed raw EthernetProceedings of: Second International Workshop on Sustainable Ultrascale Computing Systems (NESUS 2015), Krakow , Poland, 10-11 September (pp. 83-93).
      3. Dolev, S., Fatourou, P., & Kosmas, E. (2013). Abort Free SemanticTM by Dependency Aware Scheduling of Transactional Instructions. 5th Workshop on the Theory of Transactional Memory TransForm/EuroTM WTTM 2013 , Jerusalem, Israel, October 13.
      4. Baryannis, G., Garefalakis, P., Kritikos, K., Magoutis, K., Papaioannou, A., Plexousakis, D., & Zeginis, Ch. (2013). Lifecycle Management of Service-based Applications on Multi-Clouds: A Research Roadmapin Proceedings of the International Workshop on Multi-cloud Applications and Federated Clouds (MultiCloud 2013). In conjunction with 4th ACM/SPEC International Conference on Performance Engineering Jointly organized by FP7-ICT projects MODAClouds, PaaSage and ARTIST, Prague, Czech Republic , 21st to 24th April 2013.
      5. Bushkov, V.B, Dziuma, D.D, Fatourou, P., & Guerraoui, R.G (2013). Snapshot Isolation Does Not Scale Either. 5th Workshop on the Theory of Transactional Memory TransForm/EuroTM WTTM 2013, Jerusalem, Israel, October 13.
      6. Ellen, F., Fatourou, P., Kosmas, E., Milani, A., & Travers, C. (2013). Wait-Free Universal Constructions that ensure Timestamp-Ignoring Disjoint-Access Parallelism. 5th Workshop on the Theory of Transactional Memory TransForm/EuroTM WTTM 2013, Jerusalem, Israel, October 13.
      7. Dolev, S., Fatourou, P., & Kosmas, E. (2013). Abort Free SemanticTM by Dependency Aware Scheduling of Transactional InstructionsProceedings of the 8th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT), Houston, TX, USA , March 17.
      8. Chinis, G., Pratikakis , P., Athanasopoulos, E., & Ioannidis, S. (2013). Practical Information Flow for Legacy Web Applications Proceedings of the 8th Workshop on Implementation, Compilation, Optimization of Object-Oriented Languages, Programs and Systems, ICOOOLPS'13 , Montpellier, France, July (pp. 17-28). ACM.
      9. Skarlatos, D, Pratikakis , P., & Pnevmatikatos, D. (2013). Towards Reliable Task Parallel Programs . 5th Workshop on Design for Reliability (DFR 2013) , January 21-23. Berlin, Germany.
      10. Akram, S., Marazakis, M., & Bilas, A. (2012). Energy Inefficiency of Operating System Layers for Data-centric Infrastructures. 2nd workshop on Systems for Future Multi-core Architectures (SFMA'12). In conjunction with Eurosys'12, April 2012. Bern, Switzerland.
      11. Chalkiadaki, M., & Magoutis, K. (2012). Managing Service Performance in NoSQL Distributed Storage Systems. Proceedings of the 7th Middleware for Next-Generation Internet Computing (MW4NG) Workshop of the 13th International Middleware Conference 2012, December 3-7. Montreal, Canada.
      12. Akram, S., Marazakis, M., & Bilas, A. (2012). NUMA Implications for Storage I/O Throughput in Modern Servers. 3rd Workshop on Computer Architecture and Operating System co-design (CAOS'12). In conjunction with the 7th International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC'12),  , January 2012. Paris, France.
      13. Pratikakis , P., Vandierendonck, H., Lyberis, S., & Nikolopoulos, D.S. (2011). A programming model for deterministic task parallelism. Proceedings of the 2011 ACM SIGPLAN Workshop on Memory Systems Performance and Correctness, MSPC '11, San Jose, California, (pp. 7-12). New York, NY, USA: ACM (978-1-4503-0794-9).
      14. Akram, S., & Bilas, A. (2011). A sleep-based communication mechanism to adapt processor utilization in distributed streaming systems. In 2nd Workshop on Computer Architecture and Operating System co-design (CAOS'11). In conjunction with the 6th International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC'11), Heraklion, Greece, January 2011.
      15. Passas, G., Katevenis, M.G.H., & Pnevmatikatos, D. (2011). VLSI Micro-Architectures for High-Radix Crossbar Schedulers. Proc. 5th ACM/IEEE Int. Symp. on Networks-on-Chip (NOCS 2011), Pittsburgh, PA, USA, 1-4 May (8 pages). (978-1-4503-0720-8).

                    Books (19)

                        Editor

                      1. Stenstrom, P., Dubois, M., Katevenis, M.G.H., Gupta, R., & Ungerer, Th. (2008). High Performance Embedded Architectures and Compilers, Third International Conference, HiPEAC 2008, Goteborg, Sweden, January 27-29, 2008, Proceedings. HiPEAC; Lecture Notes in Computer ScienceVol. 4917 Springer, (ISBN 978-3-540-77559-1).
                      2. Sauveron, D., Markantonakis, C., Bilas, A., & Quisquater, J.J. (2007). Information Security Theory and Practices. Smart Cards, Mobile and Ubiquitous Computing Systems, First IFIP TC6 / WG 8.8 / WG 11.2 International Workshop, WISTP 2007, Heraklion, Crete, Greece, May 9-11, 2007, Proceedings. WISTP; Lecture Notes in Computer ScienceVol. 4462 Springer, (ISBN 978-3-540-72353-0).
                      3. Talia, D., Bilas, A., & Dikaiakos, M. (2007). Knowledge and Data Management in GRIDs.  (pp. 254), Vol. XVIII Springer, (ISBN 978-0-387-37830-5).
                        Chapters (in book)

                      1. Fatourou, P., Iaremko, M., Kanellou, E.K., & Kosmas, E. (2015). Algorithmic Techniques in STM DesignTransactional Memory. Foundations, Algorithms, Tools, and Applications : COST Action Euro-TM IC1001Vol. 8913 (pp. 101 - 126), Springer, (ISBN 978-3-319-14719-2 (Print) 978-3-319-14720-8 (Online)).
                      2. Fatourou, P., & Dziuma, D.D, Kanellou, E.K. (2015). Consistency for Transactional Memory Computing Transactional Memory. Foundations, Algorithms, Tools, and Applications : COST Action Euro-TM IC1001Vol. 8913 (pp. 3 - 31), Springer, (ISBN 978-3-319-14719-2 (Print) 978-3-319-14720-8 (Online)).
                      3. Attiya, H., & Fatourou, P. (2015). Disjoint-Access Parallelism in Software Transactional MemoryTransactional Memory. Foundations, Algorithms, Tools, and Applications : COST Action Euro-TM IC1001Vol. 8913 (pp. 72 - 97), Springer, (ISBN 978-3-319-14719-2 (Print) 978-3-319-14720-8 (Online)).
                      4. Nou, R. , Cortes, T., Mavridis, S., & Sfakianakis, Y.S, Bilas, A. (2014). Multi/many core. High performance parallel I/O, Series: Chapman & Hall/CRC Computational Science. Chapter 32 (pp. 353 - 362), CRC Press, (ISBN 9781466582347).
                      5. Kavadias, S.G., Katevenis, M.G.H., & Pnevmatikatos, D. (2011). Network Interface Design for Explicit Communication in Chip Multiprocessors. Designing Network-on-Chip Architectures in the Nanoscale Era, J. Flich and D. Bertozzi (Eds.).  (pp. 325 - 351), (ISBN 978-1-4398-3710-8).
                      6. Kornaros, G., Papaefstathiou, I., & Pnevmatikatos, D. (2009). Real-time Monitoring and Diagnostic Services for Networks-on-Chip. Networks-on-chips: theory and practice.  (9) Taylor & Francis Group LLC - CRC Press, (ISBN 1420079786).
                      7. Luna, J., Dikaiakos, M., Gjermundrod, H., Flouris, M.D., Marazakis, M., & Bilas, A. (2009). Using the gLite middleware to implement a secure Intensive Care Grid System.  Springer.
                      8. Német, Z., Flouris, M.D., Lachaize, R., & Bilas, A. (2007). Conductor: Support for Autonomous Configuration of Storage Systems.  (pp. 67 - 81).
                      9. Katevenis, M.G.H. (2007). Interprocessor Communication seen as Load-Store Instruction Generalization. The Future of Computing, essays in memory of Stamatis Vassiliadis. 28 Sep. (pp. 55 - 68), Delft, The Netherlands, (ISBN 978-90-807957-3-0).
                      10. Flouris, M.D., Lachaize, R., & Bilas, A. (2007). Violin: A Framework for Extensible Block-Level Storage.  (pp. 83 - 98).
                      11. Danalis, A., & Markatos, E.P. (2001). Web Caching: A Survey. Enterprise Networking: Multilayer Switching and Applications. .
                      12. Markatos, E.P., & Leblanc, Th.J. (1999). Multiprogramming and Multiprocessing. Wiley Encyclopedia of Electrical and Electronics Engineering. .
                      13. Flouris, M.D., & Markatos, E.P. (1999). Network RA, in High Performance Cluster Computing: Architectures and Systems. High Performance Cluster ComputingVol. 1, Architectures and Systems (pp. 383 - 408), Upper Saddle River, NJ: Prentice Hall PTR.
                      14. Markatos, E.P., & Leblanc, Th.J. (1996). Locality-Based Scheduling in Shared-Memory Multiprocessors. In Parallel Computing: Paradigms and Applications.  (8) (pp. 237 - 276), International Thomoson Computer Press, (ISBN 1-85032188-4).
                      15. Katevenis, M.G.H. (1995). RISC Architectures. In Parallel and Distributed Computing Handbook.  McGraw-Hill, (ISBN 0-07-073020-).
                      16. Markatos, E.P. (1994). How Architecture Evolution Influences the Scheduling Discipline used in Shared-Memory Multiprocessors. Parallel Computing: Trends and Applications, PARCO '93.  (pp. 627 - 630), Grenoble, France: Elsevier.

                            Periodicals (102)

                              Journal Articles

                            1. Fatourou, P., Nikolakopoulos, Y., & Papatriantafilou, M. (2017). Linearizable Wait-Free Iteration Operations in Shared Double-Ended QueuesParallel Processing Letters27(2), World Scientific.
                            2. Fatourou, P., & Kallimanis, N. (2017). Lower and upper bounds for single-scanner snapshot implementationsDistributed Computing30(4), 231-260, Springer .
                            3. Charitopoulos, G., Koidis, L., Papadimitriou, K., & Pnevmatikatos, D. (2017). Run-time management of systems with partially reconfigurable FPGAsIntegration, the VLSI Journal57, 34-44, Elsevier.
                            4. Theodoropoulos, D., Mazumdar, S., Ayguade, E., Bettin, N., Bueno, J., Ermini, S., Filgueras, A, Jimenez-Gonzalez, D., Alvarez-Martinez, C., Martorell, X., Montefoschi, F., Oro, D., Pnevmatikatos, D., Rizzo, A., Gai, P., Garzarella, S., Morelli, B., Pomella, A., & Giorgi , R. (2017). The AXIOM platform for next-generation cyber physical systemsMicroprocessors and Microsystems52(July), 540-555, Elsevier.
                            5. Papagiannis, A., Saloustros, G., Marazakis, M., & Bilas, A. (2016). Iris: An optimized I/O stack for low-latency storage devicesACM SIGOPS Operating Systems Review50(3), 3-11, ACM.
                            6. Chrysos, N., Chen, L., Kachris, C., & Katevenis , M. (2016). Discharging the Network From Its Flow Control Headaches: Packet Drops and HOL BlockingIEEE/ACM Transactions on Networking 24(1), 15-28, IEEE.
                            7. Gonzalez-Ferez, P., & Bilas, A. (2016). Mitigation of NUMA and synchronization effects in high-speed network storage over raw EthernetThe Journal of Supercomputing72(11), 4129-4159, Springer .
                            8. Giorgi , R., Mazumdar, S., Viola, S., Gai, P., Garzarella, S., Morelli, B., Pnevmatikatos, D., Theodoropoulos, D., Alvarez , C., Ayguade, E., Bueno, J., Filgueras, A, Jimenez-Gonzalez, D., & Martorell, X. (2016). Modeling Multi-board Communication in the AXIOM Cyber-Physical System. Ada User Journal37(4), 228-235.
                            9. Alvarez , C., Ayguade, E., Bosch , J., Bueno, J., Cherkashin, A., Filgueras, A, Jimenez-Gonzalez, D., Martorell, X., Navarro, N., Vidal, M., Theodoropoulos, D., Pnevmatikatos, D., Catani, D., Oro, D., Fernandez, C., Segura , C., Rodriguez Saeta, J., Hernando, J., Scordino, C., Gai, P., Passera, P., Pomella, A., Bettin, N., Rizzo, A., & Giorgi , R. (2016). The AXIOM software layersMicroprocessors and Microsystems47 Part B, 262-277, Elsevier.
                            10. Ellen, F., Fatourou, P., Kosmas, E., Milani, A., & Travers, C. (2016). Universal Constructions that Ensure Disjoint-Access Parallelism and Wait-FreedomDistributed Computing 29(4), 251-277, Springer.
                            11. Fatourou, P., Kanellou, E.K., & Eleftherios , K. , Rabbi, M. F. (2016). WFR-TM: Wait-free readers without sacrificing speculation of writersJournal of Parallel and Distributed Computing96, 134-151, Springer .
                            12. Pnevmatikatos, D., Papadimitriou, K., Becker, T., Böhm , P., Brokalakis, A., Bruneel, K., Ciobanu, C.B., Davidson, T., Gaydadjiev, G., Heyse, K., Luk, W., Niu, X., Papaefstathiou, I., Pau, D., Pell, O., Pilato, C., Santambrogio, M.D., Sciuto, D., Stroobandt, D., Todman, T., & Vansteenkiste, E. (2015). FASTER: Facilitating Analysis and Synthesis Technologies for Effective ReconfigurationMicroprocessors and Microsystems39(4-5), 321-338, Elsevier.
                            13. Passas, G., Katevenis, M.G.H., & Pnevmatikatos, D. (2015). The Combined Input-Output Queued Crossbar Architecture for High-Radix On-Chip SwitchesIEEE Micro35(6), 38 -47, IEEE.
                            14. Manousakis, I., Zakkak, F. S., Pratikakis , P., & Nikolopoulos, D.S. (2015). TProf: An energy profiler for task-parallel programsSustainable Computing: Informatics and Systems5, 1-13, Elsevier.
                            15. Kitsos, I., Magoutis, K., & Tzitzikas, Y. (2014). Scalable entity-based summarization of web search results using MapReduce Distributed and Parallel Databases32(3), 405-446, Springer.
                            16. Dziuma, D.D, Fatourou, P., & Kanellou, E.K. (2014). Consistency for Transactional Memory ComputingBulletin of the EATCS 113.
                            17. Symeonidou, C., Pratikakis , P., Nikolopoulos, D.S., & Bilas, A. (2014). Distributed region-based memory allocation and synchronizationInternational Journal of High Performance Computing Applications28(4), 406-414 , ACM.
                            18. Lyberis, S., Kalokairinos, G., Lygerakis , M., Papaefstathiou, V., Mavroidis, I., Katevenis, M.G.H., Pnevmatikatos, D., & Nikolopoulos, D.S. (2014). FPGA prototyping of emerging manycore architectures for parallel programming research using Formic boardsJournal of Systems Architecture (JSA)60(6), 481-493, Elsevier.
                            19. Fatourou, P., & Kallimanis, N. (2014). Highly-Efficient Wait-Free SynchronizationTheory of Computing Systems55(3), 475-520, Springer.
                            20. Papagiannis, A., & Nikolopoulos, D.S. (2014). Hybrid address spaces: A methodology for implementing scalable high-level programming models on non-coherent many-core architectures Journal of Systems and Software97, 47-64, Elsevier.
                            21. Sourdis, I., Strydis, C., Armato , A., Bouganis, C.S., Falsafi, B., Gaydadjiev, G.N., Isaza, S., Malek, A., Mariani, R., Pnevmatikatos, D., Pradhan , D.K., Rauwerda, G., Seepers, R.M., Shafik, R.A., Sunesen, K., Theodoropoulos, D., Tzilis, S., & Vavouras, M. (2013). DeSyRe: On-demand system reliabilityMicroprocessors and Microsystems: Embedded Hardware Design37(8-C), 981-1001, Elsevier.
                            22. Kachris, C., Nikiforos, G., Papaefstathiou, V., Kavadias, S.G., & Katevenis, M.G.H. (2013). NP-SARC: Scalable network processing in the SARC multi-core FPGA platformJournal of Systems Architecture (JSA)59(1), 39-47, Elsevier.
                            23. Kornaros, G., & Pnevmatikatos, D. (2013). A survey and taxonomy of on-chip monitoring of multicore systems-on-chipACM Transactions on Design Automation of Electronic Systems (TODAES)18(2), 17:1-17:38, ACM Press.
                            24. Kavadias, S.G., Katevenis, M.G.H., Zampetakis, L.A., & Nikolopoulos, D.S. (2012). Cache-Integrated Network Interfaces: Flexible On-Chip Communication and Synchronization for Large-Scale CMPs. International Journal of Parallel Programming (IJPP)40(6), 583-604, Springer (1573-7640).
                            25. Passas, G., Katevenis, M.G.H., & Pnevmatikatos, D. (2012). Crossbar NoCs Are Scalable Beyond 100 Nodes. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)31(4), 573-585, (ISSN0278-0070).
                            26. Suarez Gracia, D., Dimitrakopoulos, G., Monreal, A., Katevenis, M.G.H., & Vinals Yufera, V. (2012). LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors. IEEE Transactions on Very Large Scale Integrated Systems (TVLSI)20(8), 1510-1523, (1063-8210), earlier published on-line: vol. PP, no. 99, July 2011.
                            27. Klonatos, Y., Makatos, A., Marazakis, M., Flouris, M.D., & Bilas, A. (2012). Transparent online storage compression at the block-level. ACM Transactions on Storage (TOS)8(2), 5:1-5:33.
                            28. Chrysos, N., & Katevenis, M.G.H. (2011). Distributed WFQ scheduling converging to weighted max-min fairness. Computer Networks: The International Journal of Computer and Telecommunications Networking 55(3), 792-806, New York, NY, USA: Elsevier North-Holland, Inc. (ISSN 1389-1286).
                            29. Attiya, H., Faith, E., & Fatourou, P. (2011). The complexity of updating snapshot objects. J. Parallel Distrib. Comput.71(12), 1570-1577, Orlando, FL, USA: Academic Press, Inc. (ISSN 0743-7315).
                            30. Ferrer, R., Bellens, P., Yeom, J.S., Schneider, Sc., Koukos, K., Alvanos, M., Beltran, V., González, M., Martorell, X., Badia, R.M., Nikolopoulos, D.S., Bilas, A., & Ayguade, E. (2010). Parallel Programming Models for Heterogeneous Multicore ArchitecturesIEEE Micro30(5), 42-53, (0272-1732).
                            31. Luna, J., Dikaiakos, M., Marazakis, M., & Kyprianou, Th. (2010). Data-centric privacy protocol for intensive care grids. , 14(6), 1327-1337, (1089-7771).
                            32. Katevenis, M.G.H., Papaefstathiou, V., Kavadias, S.G., Pnevmatikatos, D., Silla, F., & Nikolopoulos, D.S. (2010). Explicit Communication and Synchronization in SARC. IEEE Micro30(5), 30-41, (0272-1732).
                            33. Flouris, M.D., Lachaize, R., Chasapis, K., & Bilas, A. (2010). Extensible block-level storage virtualization in cluster-based systems. Journal of Parallel and Distributed Computing70(8), 800-824, (07437315).
                            34. Kalokairinos, G., Papaefstathiou, V., Nikiforos, G., Kavadias, S.G., Katevenis, M.G.H., Pnevmatikatos, D., & Yang, X. (2010). Prototyping a Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability. Transactions on HiPEAC5(3), Springer Berlin Heidelberg.
                            35. Chrysos, N.I., & Dimitrakopoulos, G. (2009). Practical high-throughput crossbar scheduling. IEEE Micro29(4), 22-35, (02721732).
                            36. Schneider, Sc., Yeom, J.S., & Nikolopoulos, D.S. (2009). Programming Multiprocessors with Explicitly Managed Memory Hierarchies. Computer42(12), 28-34, Los Alamitos, CA, USA: IEEE Computer Society Press (0018-9162).
                            37. Rafique, M.M., Rose, B., Butt, A.R., & Nikolopoulos, D.S. (2009). Supporting MapReduce on large-scale asymmetric multi-core clusters. SIGOPS Oper.Syst.Rev.43(2), 25-34, New York, NY, USA: ACM (0163-5980).
                            38. Simos, D.G., Papaefstathiou, I., & Katevenis, M.G.H. (2008). Building an FoC using large, buffered crossbar cores. IEEE Design and Test of Computers25(6), 538-548, (07407475).
                            39. Sourdis, I., Pnevmatikatos, D., & Vassiliadis, S. (2008). Scalable multigigabit pattern matching for packet inspection. IEEE Trans Very Large Scale Integr VLSI Syst16(2), 156-166, (10638210).
                            40. Manifavas, C., Papaefstathiou, I., & Sotiriou, Ch.P. (2007). High throughput, low power implementations for the DES family. WSEAS Trans.Comput.6(3), 532-538, (11092750).
                            41. Bosschere, K., Luk, W., Martorell, X., Navarro, N., O"Boyle, M., Pnevmatikatos, D., Ramirez, A., Sainrat, P., Seznec, A., Stenstrom, P., & Temam, O. (2007). High-Performance Embedded Architecture and Compilation Roadmap. , 4050, 5-29, Berlin / Heidelberg: Springer (978-3-540-71527-6).
                            42. Ioannou, A., & Katevenis, M.G.H. (2007). Pipelined heap (priority queue) management for advanced scheduling in high-speed networks. IEEE/ACM Transactions on Netwoking15(2), 450-461, (1063-6692).
                            43. Cortadella, J., Kondratyev, A., Lavagno, L., & Sotiriou, Ch.P. (2006). Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on25(10), 1904-1921, (0278-0070).
                            44. Dobkin, R., Ginosar, R., & Sotiriou, Ch.P. (2006). High rate data synchronization in GALS SoCs. IEEE Trans Very Large Scale Integr VLSI Syst14(10), 1063-1074, (10638210).
                            45. Sapountzis, G., & Katevenis, M.G.H. (2005). Benes switching fabrics with O(N)-Complexity internal backpressure. IEEE Communications Magazine43(1), 88-94, (01636804).
                            46. Zhou, Y., Bilas, A., Jagannathan, S., Xinidis, D., Dubnicki, C., & Li, K. (2005). VI-attached database storage. IEEE Trans Parallel Distrib Syst16(1), 35-50, (10459219).
                            47. Dobkin, R., Ginosar, R., & Sotiriou, Ch.P. (2004). Data synchronization issues in GALS SoCs. Proc.Int.Symp.Adv.Res.Asynchr.Circuits.Syst.10, 170-179, (15228681).
                            48. Papaefstathiou, I., Papaefstathiou, V., & Sotiriou, Ch.P. (2004). Design-space exploration of the most widely used cryptography algorithms. Microprocessors Microsyst28(10), 561-571, (01419331).
                            49. Blunno, I., Cortadella, J., Kondratyev, A., Lavagno, L., Lwin, K., & Sotiriou, Ch.P. (2004). Handshake protocols for de-synchronization. Proc.Int.Symp.Adv.Res.Asynchr.Circuits.Syst.10, 149-158, (15228681).
                            50. Sotiriou, Ch.P., Ginosar, R., Stevens, K., Lavagno, L., & Heer, C. (2004). Message from the chairs. Proc.Int.Symp.Adv.Res.Asynchr.Circuits.Syst.10, (15228681).
                            51. Papaefstathiou, I., Perissakis, S., Orphanoudakis, T.G., Nikolaou, N.A., Kornaros, G., Zervos, N.A., Konstantoulakis, G., Pnevmatikatos, D., & Vlachos, K. (2004). PRO3: A hybrid NPU architecture. IEEE Micro24(5), 20-33, (02721732).
                            52. Pnevmatikatos, D., Sourdis, I., & Vlachos, K. (2003). An efficient, low-cost I/O subsystem for network processors. IEEE Des Test Comput20(4), 56-64, (07407475).
                            53. Sartzetakis, S., Tziouvaras, Ch.I., & Georgiadis, L. (2002). Adaptive routing algorithm for lambda switching networks. Optical Networks Magazine3, 476-487.
                            54. Markatos, E.P., Papachristos, Ch., & Dramitinos, G. (2002). Web-based Infrastructure for Tourism Information Systems. Informatics and Telematics, Elsevier Science (ISSN: 0736-5853).
                            55. Markatos, E.P., Pnevmatikatos, D., Flouris, M.D., & Katevenis, M.G.H. (2002). Web-conscious storage management for Web proxies. IEEE/ACM Transactions on Networking10(6), 735-748, (1063-6692).
                            56. Ioannidis, S., Papathanasiou, A E., Magklis, G.I., Markatos, E.P., Pnevmatikatos, D., & Sevaslidou, J.E. (2001). On using reliable network RAM in networks of workstations. , 109-120, Commack, NY, USA: Nova Science Publishers, Inc (1-59033-113-3).
                            57. Katevenis, M.G.H., Sapountzis, G., Kalyvianaki, E., Mavroidis, I., & Glykopoulos, G. (2001). Wormhole IP over (connectionless) ATM. IEEE/ACM Transactions on Networking9(5), 650-661, (10636692).
                            58. Dramitinos, G., & Markatos, E.P. (1999). Adaptive and Reliable Paging to Remote Main Memory. J.Parallel Distrib.Comput.58(3), 357-388, (07437315).
                            59. Kornaros, G., Pnevmatikatos, D., Vatsolaki, P., Kalokairinos, G., Xanthaki, Ch., Mavroidis, D., Serpanos, D.N., & Katevenis, M.G.H. (1999). ATLAS I: Implementing a single-chip ATM switch with backpressure. IEEE Micro19(1), 30-40, (02721732).
                            60. Pnevmatikatos, D., Markatos, E.P., Magklis, G.I., & Ioannidis, S. (1999). On using network RAM as a non-volatile buffer. Cluster Computing2(4), 295-303,.
                            61. Ioannidis, S., Papathanasiou, A E., Magklis, G.I., Markatos, E.P., Pnevmatikatos, D., & Sevaslidou, J.E. (1999). On Using Reliable Network RAM in Networks of WorkstationsParallel and Distributed Computing Practices2(2), (1097-2803).
                            62. Katevenis, M.G.H., Markatos, E.P., Vatsolaki, P., & Xanthaki, Ch. (1999). Remote Enqueue Operation on Networks of Workstations. Informatica - An International Journal of Computing and Informatics23(1), 29-39, (03505596).
                            63. Flouris, M.D., & Markatos, E.P. (1999). The Network RamDisk: Using remote memory on heterogeneous NOWs. Cluster Computing2(4), 281-293.
                            64. Papathanasiou, A E., Papadakakis, N., & Markatos, E.P. (1999). Visualizing Traffic on the World Wide WebWebNet Journal: Internet Technologies, Applications & Issues1(2), 57-65, Charlottesville, VA: AACE (1522-192X).
                            65. Markatos, E.P., & Chronaki, C. (1998). A TOP-10 approach to prefetching on Web. Proceedings of INET"98.
                            66. Katevenis, M.G.H., Serpanos, D.N., & Dimitriadis, G. (1998). ATLAS I: A single-chip, gigabit ATM switch with HIC/HS links and multi-lane back-pressure. Microprocessors and Microsystems21(7-8), 481-490, (01419331).
                            67. Nastou, P.E., Serpanos, D.N., & Maritsas, D.G. (1998). Average case analysis of searching in associative processing. J.Parallel Distrib.Comput.54(2), 133-161, Orlando, FL, USA: Academic Press, Inc (0743-7315).
                            68. Serpanos, D.N., Tantawi, A.N., & Tantawy, A.N. (1998). Credit scheduling: adaptive scheduling with dynamic service quota. Computer Communications21(10), 889-897, (0140-3664).
                            69. Serpanos, D.N., Georgiadis, L., & Bouloutas, T. (1998). MMPacking: a load and storage balancing algorithm for distributed multimedia serversIEEE Transactions on Circuits and Systems for Video Technology8(1), 13, (1051-8215).
                            70. Katevenis, M.G.H., Markatos, E.P., Kalokairinos, G., & Dollas, A. (1997). Telegraphos: a substrate for high-performance computing on workstation clustersJournal of Parallel and Distributed Computing43(2), 94-108, (0743-7315).
                            71. Serpanos, D.N., Katevenis, M.G.H., & Spyridakis, E. (1997). ATLAS I: building block for ATM networks with credit-based flow control. , 162-167.
                            72. Houstis, C.E., Kapidakis, S., Markatos, E.P., & Gelenbe, E. (1997). Execution of compute-intensive applications into parallel machines. Information Sciences97(1-2), 83-124, (0020-0255).
                            73. Markatos, E.P. (1997). VISUALIZING WORKING SETS. Operating systems review.31(4), 3, New York, N.Y.: ACM Special Interest Group on Operating Systems] (0163-5980).
                            74. Bisdikian, C., Maruyama, K., Seidman, D.I., & Serpanos, D.N. (1996). Cable access beyond the hype: on residential broadband data services over HFC networks. IEEE Communications Magazine34(11), 128-135.
                            75. Katevenis, M.G.H., Vatsolaki, P., & Chalkiadakis, V. (1996). Credit-flow-controlled ATM over HIC links in the ASICCOM "ATLAS I" single-chip switch. Real-Time Magazine, 65-72.
                            76. Markatos, E.P. (1996). Main memory caching of Web documents. Computer Networks and ISDN Systems28(7-11), 893-905, (0169-7552).
                            77. Markatos, E.P., & Chronaki, C. (1994). Trace-Driven Simulation of Data-Alignment and Ohter Factors Affecting Update and Invalidate Based Coherent Memory. , 44-51,, IEEE Computer Society (0-8186-5292-6).
                            78. Katevenis, M.G.H., Sidiropoulos, S., & Courcoubetis, C. (1991). Weighted round-robin cell multiplexing in a general-purpose ATM switch chip. IEEE J Sel Areas Commun9(8), 1265-1279, (07338716).
                            79. Katevenis, M.G.H. (1987). Fast Switching and Fair Control of Congested Flow in Broadband Networks . IEEE Journal on Selected Areas in Communications (JSAC)5(8), 1315-1326, (07338716).
                                  Magazine article

                                1. Bilas, A., & Bitzou, Th. (2012). More data? Yes, thank you!. The Economist (Kathimerini), (97), 36.
                                2. Katevenis, M.G.H. (2011). Ιδρύεται το Ευρωπαϊκό Κέντρο Αρχιτεκτονικής Υπολογιστών EuRECCA.  E&T Magazine of GSRT.
                                3. Fatourou, P. (2011). ΤransForm: Θεωρητικές θεμελιώσεις των συστημάτων συγχρονισμού διεργασιών μέσω δοσοληψιών.  E&T Magazine of GSRT.
                                4. Flouris, M.D., & Bilas, A. (2010). Nαυαγοί στον ωκεανό της πληροφορίας. The Economist (Kathimerini)5(76), 46-47.
                                    Newsletters articles

                                  1. Zakkak, F. S., & Pratikakis , P. (2014). JDMM: a java memory model for non-cache-coherent memory architecturesACM SIGPLAN Notices 49(11), 83-92, ACM.
                                    ERCIM News

                                  1. Jimenez-Peris, R., Patino-Martinez, M., Magoutis, K., Bilas, A., & Brondino, I. (2012). CumuloNimbo: A High-Scalable Transaction Processing Platform as a ServiceERCIM News89, 34-35, April.
                                  2. Jimenez-Peris, R., Patino-Martinez, M., Magoutis, K., & Bilas, A. (2012). CumuloNimbo: A Highly-Scalable Transaction Processing Platform as a Service. , 89, 34-35, April.
                                  3. Bilas, A. (2010). IOLanes: Advancing the Scalability and Performance of I/O Subsystems in Multicore PlatformsERCIM News82, 54-55, July 2010.
                                  4. Mangas, E., & Bilas, A. (2009). FLASH: Fine-Grained Localization in Wireless Sensor NetworksERCIM News76, 42-43, January 2009.
                                  5. Nikolopoulos, D.S. (2009). Green Building Blocks - Software Stacks for Energy-Efficient Clusters and Data CentresERCIM News79, 13, July 2009.
                                  6. Nikolopoulos, D.S. (2008). Set-Top Supercomputing: Scalable Software for Scientific Simulations on GameConsolesERCIM News74, 44-45, July 2008.
                                  7. Luna, J., Dikaiakos, M., & Marazakis, M. (2008). Using Desktop Grids to Securely Store e-Health DataERCIM News74, 32-33, July 2008.
                                  8. Kapelonis, K., Karsson, S., & Bilas, A. (2006). TPC: Tagged Procedure CallsERCIM News67, 30-31, October 2006.
                                  9. Baltzakis, H., Bilas, A., & Trahanias, P.E. (2005). iWATCH: Intelligent Watch Based on Networked Smart Sensors and Autonomous Mobile VehiclesERCIM News63, 17-18, October 2005.
                                  10. Katevenis, M.G.H., & Chrysos, N.I. (2004). New Crossbar Directly Switches Variable-Size PacketsERCIM News57, 58-59, April 2004.
                                  11. Bilas, A., & Markatos, E.P. (2003). Wearable Systems for Everyday UseERCIM News52, 15-16, January 2003.
                                  12. Markatos, E.P. (2001). ServerGrids: Available and Scalable Global Computing PlatformsERCIM News45, April 2001.
                                  13. Pnevmatikatos, D. (1999). High-Performance ATM Switching: the ATLAS I Single Chip SwitchERCIM News37, April 1999.
                                  14. Markatos, E.P., & Papathanasiou, A E. (1999). Monitoring and Displaying Traffic on the World Wide WebERCIM News37, April 1999.
                                  15. Markatos, E.P. (1998). TeachWEB - Novel Learning Approaches using the World-Wide WebERCIM News33, April 1998.
                                  16. Markatos, E.P., & Chronaki, C. (1996). Caching, Prefetching and Coherence in the World Wide WebERCIM News25, April 1996.
                                  17. Nikolaou, Ch., Saridakis, T., & Markatos, E.P. (1995). ArrayTracerERCIM News23, April 1995.
                                  18. Katevenis, M.G.H., & Georgis, Ch. (1995). The Labyrinth System. , 20, January 1995.

                                      Talks (15)

                                        Distinguished Lectures

                                      1. Fatourou, P. (2017). Concurrency for the masses: the Paradigm of Transactional Memory. South East European University, FYROM, February 23, 2017, February 23.
                                      2. Fatourou, P. (2017). Concurrency for the masses: the Paradigm of Transactional Memory. 19th International Symposium on Symbolic and Numeric Algorithms for Scientific Computing, Timisoara, Romania, September 21-24.
                                      3. Fatourou, P. (2017). Harnessing the Difficulties of Synchronization. Ss. Cyril and Methodius University - Skopje, Faculty of Computer Science and Engineering, February 24.
                                      4. Katevenis, M.G.H. (2008). Towards Unified Mechanisms for Inter-Processor Communication.  IEEE Int. Conf. on Embedded Computer Systems: Architectures, Modeling and Simulation, Samos, Greece, 21-24 July.
                                        Invited Talks

                                      1. Pratikakis , P. (2013). The Formic Architecture and the Myrmics Runtime System Berlin, Germany, . ENCORE & PEPPHER Workshop on Programmability and Portability for Emerging Architectures (EPoPPEA’13), January , Berlin, Germany.
                                      2. Pratikakis , P. (2012). Distributed Region-Based Memory Management . University of Maryland, College Park, August .
                                      3. Magoutis, K. (2012). Recent Advances in Large-scale IT Service Management Technologies. 6th Advanced School on Service Oriented Computing , July 2- 7, Hersonissos, Crete, Greece.
                                      4. Bilas, A. (2012). Scaling I/O in Virtualized Muticore Servers: How much I/O in 10 years and how to get there . Invited Talk: The 6th International Workshop on Virtualization Technologies in Distributed Computing (VTDC'12), June 19, Delft, The Netherlands, in conjunction with the 21th edition of HPDC'12 .
                                      5. Bilas, A. (2012). Server Storage I/O: How Much I/O and How To Get There . Intel European Research and Innovation Conference 2012 - Intel ERIC , October 22-23, Barcelona, Spain.
                                      6. Katevenis, M.G.H. (2012). Task Parallelism, Explicit Communication, and Architectural Support for them. Nano-Tera/Artist Summer School on Embedded System Design, Aix-les-Bains, France, 17-21 Sep..
                                      7. Katevenis, M.G.H. (2011). Informatics High Technology as a Tool in Medicine. Medical School Graduation Ceremony, University of Crete, Heraklion, Greece, 15 July.
                                      8. Katevenis, M.G.H. (2010). Replicate and Migrate Objects in the Runtime, not Cache Lines or Pages in Hardware. Barcelona Multicore Workshop 2010, Barcelona, Spain, 21-22 Oct.
                                      9. Katevenis, M.G.H. (2007). Interprocessor Communication seen as Load-Store Instruction Generalization. Stamatis Vassiliadis Symposium - The Future of Computing, Delft, The Netherlands, 28 Sep..
                                      10. Katevenis, M.G.H. (2006). Towards Light-Weight Intra-CMP Network Interfaces. Workshop on On- and Off-Chip Interconnection Networks for Multicore Systems, Stanford, California, USA, 6-7 Dec.
                                      11. Katevenis, M.G.H. (1993). Parallel Computer Architecture: Shared Memory versus Message Passing. Symposium of the European Research Consortium for Informatics and Mathematics (ERCIM), Rutherford Appleton Laboratory, UK, 10-12 November.

                                        Technical & Research Reports (210)

                                            Miscalleneous

                                          1. Klonatos, Y. (2011). Design and Evaluation of Solid-State Drive (SSD) Caches to Improve Storage I/O PerformanceΣχεδιασμός και Αξιολόγηση Κρυφών μνημών με Solid-State Drives (SSD)για τη βελτίωση της απόδοσης της Ε/Ε αποθήκευσης
                                            ICS-FORTH Technical Reports

                                          1. Zakkak, F. S. (2017). Java on Scalable Memory Architectures. 2017.TR464_JAVA_on_Scalable_Memory_Architectures.pdf.
                                          2. Fatourou, P., Kallimanis, N., Kanellou, E.K., Makridakis, O., & Symeonidou, C. (2015). Distributed data structures for future many-core architectures. 2015.TR447.Apr2015.pdf.
                                          3. Poulios, P.D. (2015). Low-Latency Implementation of Network Sockets over Remote DMA. 2015.TR455_Low-Latency_Network_Sockets_Remote_DMA.pdf.
                                          4. Velegrakis, J.V. (2015). Operating System Mechanisms for Remote Resource Utilization in ARM Microservers. 2015.TR452_Operating_System_Mechanisms_ARM_Microservers.pdf.
                                          5. Kallimanis, N., & Fatourou, P. (2014). The Power of Scheduling-Aware Synchronization. 2014.TR442_Scheduling-Aware_Synchronization.pdf.
                                          6. Sfakianakis, Y.S, Mavridis, S., Fountoulakis, M., Papageorgiou, S.P, Chasapis, K., Papagiannis, A., Marazakis, M., & Bilas, A. (2014). Vanguard:Increasing Server Utilization via Workload Isolation in the Storage I/O Path. TR446_Vanguard_Increasing_Server_Utilization_Storage.pdf.
                                          7. Lyberis, S. (2013). Myrmics: A Scalable Runtime System for Global Address Spaces. 2013.TR436_Myrmics_Scalable_Runtime_System_Global_Address_Spaces.pdf.
                                          8. Bushkov, V.B, Fatourou, P., & Dziuma, D.D, Guerraoui, R.G (2013). Snapshot Isolation Does Not Scale Either. 2013.TR437_Snapshot_Isolation_Does_Not_Scale_Either.pdf.
                                          9. Dziuma, D.D, Fatourou, P., & Kanellou, E.K. (2013). Survey on consistency conditions. 2013.TR439_Survey_on_Consistency_Conditions.pdf.
                                          10. Tzenakis, G., Papatriantafyllou, A., Zakkak, F. S., Vandierendonck, H., Pratikakis , P., & Nikolopoulos, D. (2012). BDDT: Block-level Dynamic Dependence Analysis for Deterministic Task-Based Parallelism. 2012 TR426_Block-level_Dynamic_Dependence_Analysis_for_Deterministic_Task-Based_Parallelism.pdf.
                                          11. Pratikakis , P., Chinis, G, Athanasopoulos, E., & Ioannidis, S. (2012). Practical Information Flow for Legacy Web Applications. 2012.TR428_Practical-Information_Flow_for_Legacy_Web_Applications.pdf.
                                          12. Lyberis, S., & Kalokairinos, G. (2012). The 512-core Formic Hardware Prototype : Architecture Manual & Programmer's Model. 2012.TR430_The_512-core_Formic_Hardware_Prototype.pdf.
                                          13. Passas, G. (2012). VLSI Micro-Architectures for High-Radix Crossbars. 2012.TR427_VLSI_Micro-Architectures_High-Radix_Crossbars.pdf.
                                          14. Tsaliagos, D. (2011). Design and Implementation of a Directory based Cache Coherence Protocol. 2011.TR418_Directory_based_Cache_Coherence_Protocol.pdf.
                                          15. Kavadias, S.G. (2010). Direct Communication and Synchronization Mechanisms in Chip Multiprocessors. 2010.TR411_Direct_Communication_Synchr_Mechanisms_Chip_Multiprocessors.pdf.
                                          16. Nikiforos, G. (2010). FPGA implementation of a cache controller with configurable scratchpad space. 2010.TR402_FPGA_Cache_Controller.pdf.
                                          17. Mihelogiannakis, G. (2007). Approaching Ideal NoC Latency with Pre-Configured Routes. 2007.TR391_Approaching_Ideal_NoC_Latency.pdf.
                                          18. Papamichael, M. (2007). Network Interface Architecture and Prototyping for Chip and Cluster Multiprocessors. 2007.TR392_Network_Interface_Architecture_Chip_Cluster_Multiprocessors.pdf.
                                          19. Chrysos, N.I. (2007). Request-Grant Scheduling for Congestion Elimination in Multistage Networks. 2007.TR388_Congestion_Elimination_Multistage_Networks.pdf.
                                          20. Apostolopoulos, G. (2006). Building Extensible and Robust Networking Systems using Virtual Machines. 2006.TR384_Extensible_Robust_Networking_Systems.pdf.
                                          21. Vlachos, E. (2006). Design and Implementation of a Coherent Memory Sub-System for Shared Memory Multiprocessors. 2006.TR382_Coherent_Memory_Sub-System_Multiprocessors.pdf.
                                          22. Kalokairinos, G., Papaefstathiou, V., Ioannou, A., Simos, D.G., Papamichail, M., Mihelogiannakis, G., Marazakis, M., Pnevmatikatos, D., & Katevenis, M.G.H. (2006). Design and Implementation of a Multi-Gigabit NIC and a Scalable Buffered Crossbar Switch. 2006.TR376_Design_Multi-Gigabit_NIC.pdf.
                                          23. Apostolopoulos, G., & Ciurea, I. (2006). Reducing the Forwarding State Requirements of Point-to-Multipoint Trees Using MPLS Multicast. 2006.TR367_Reducing_Requirements_Point-to-Multipoint_Trees.pdf.
                                          24. Flouris, M.D., Lachaize, R., & Bilas, A. (2006). Shared & Flexible Block I/0 for Cluster-Based Storage. 2006.TR380_Shared_Flexible_Block_Cluster-Based_Storage.pdf.
                                          25. Apostolopoulos, G. (2006). Using Multiple Topologies for IP-only Protection Against Network Failures: A Routing Performance Perspective. 2006.TR377_Routing_Performance_Perspective.pdf.
                                          26. Apostolopoulos, G., & Chasapis, K. (2006). V-eM: A Cluster of Virtual Machines for Robust, Detailed, and High-Performance Network Emulation. 2006.TR371_V-eM_Cluster_of_Virtual_Machines.pdf.
                                          27. Matthaiakis, P. (2005). Study of the inter and intra die variability of the SPARTAN 2E FPGA using dual rail circuits. 2005.TR361_Spartan_2E_FPGA_using_dual_rail_circuits.pdf.
                                          28. Kounalakis, E. (2005). The Mythical IP Block: An Investigation of Contemporary IP Characteristics. 2005.TR366.Mythical_IP_Block.pdf.
                                          29. Andrikos, N. (2004). Automated Flow for Digital Circuits De-synchronization. 2004.TR338_Automated_Flow_for_Digital_Circuits_De-synchronization.pdf.
                                          30. Simos, D.G. (2004). Design of a 32x32 Variable-Packet-Size Buffered Crossbar Switch Chip. 2004.TR339_Variable_Packet-Size_Buffered_Crossbar_Switch_Chip.pdf.
                                          31. Vlachos, E. (2004). Study of asynchronous controllers" circuits in de-synchronized systems. 2004.TR337_Asynchronous_Controllers"_Circuits.pdf.
                                          32. Flouris, M.D., & Bilas, A. (2004). Violin: A Framework for Extensible Block-level Storage. 2004.TR344_Violin_Framework_Extensible_Block-level_Storage.pdf.
                                          33. Kokkalis, N.P. (2003). A Switching Fabric Simulator Accelerator using a systolic array of FPGA"s. 2003.TR321.Switching_Fabric_Simulator_Accelerator_using.FPGAs.pdf.
                                          34. Flouris, M.D., & Bilas, A. (2003). Clotho: Transparent Data Versioning at the Block I/O Level. 2003.TR326_Clotho_Transparent_Data_Versioning.pdf.
                                          35. Chrysos, N.I. (2003). Design Issues of Variable-Packet-Size, Multiple-Priority Buffered Crossbars. 2003.TR325_Multiple-priority_Buffered_Crossbars.pdf.
                                          36. Passas, G. (2003). Performance Evaluation of Variable Packet Size Buffered Crossbar Switches. 2003.TR328_Evaluation_Packet-Size_Buffered_Crossbar_Switches.pdf.
                                          37. Antonatos, S., Anagnostakis, K.G., Markatos, E.P., & Polychronakis, M. (2002). Benchmarking and Design of String Matching Intrusion Detection Systems. 2002.TR315.benchmarking_ids.ps.gz.
                                          38. Sapountzis, G., & Katevenis, M.G.H. (2002). Benes Fabrics with Internal Backpressure: First Work-in-Progress Report. 2002.TR303.Benes_Fabrics_Internal_Backpressure.ps.gz.
                                          39. Sapountzis, G. (2002). Benes Switching Fabrics with 0(N)-Complexity Internal Backpressure. 2002.TR316.Bennes_Switching_Fabrics_Complexity_Internal_Backpressure.pdf.gz.
                                          40. Kapsalis, D. (2002). Design and implementation of a per-flow queue manager for an ATM switch using FPGA Technology. 2002.TR302.Design_per_flow_queue_manager_FPGA_Technology.ps.gz.
                                          41. Sotiriou, Ch.P. (2002). Direct-Mapped Asynchronous Finite-State Machines in CMOS Technology. 2002.TR305.Direct-Mapped_Asynchronous_CMOS_Technology.pdf.gz.
                                          42. Anagnostakis, K.G., Antonatos, S., Markatos, E.P., & Polychronakis, M. (2002). E2 XB: A Domain-Specific String Matching Algorithm for Intrusion Detection. 2002.TR311.Domain_String_Matching_Algorithm_Intrusion_Detection.ps.gz.
                                          43. Markatos, E.P., Antonatos, S., Polychronakis, M., & Anagnostakis, K.G. (2002). Exclusion-based signature matching for intrusion detection. 2002.TR310.String_Matching_for_Intrusion_Detection.ps.gz.
                                          44. Sotiriou, Ch.P. (2002). Implementing Asynchronous Circuits using a Conventional EDA Tool-Flow. 2002.TR306.Asynchronous_Circuits_using_Conventional_EDA_Tool-Flow.pdf.gz.
                                          45. Portokalidis, G., Markatos, E.P., & Marazakis, M. (2002). Study and Bridging of Peer-to-Peer File Sharing Systems. 2002.TR312.Bridging_Peer-to-Peer_File_Sharing_Systems.pdf.gz.
                                          46. Chrysos, N.I., & Katevenis, M.G.H. (2002). Weighted Max-Min Fair Scheduling for an Input-Buffered Crossbar Switch, with Small Internal Memory. 2002.TR309.Max_Min_Fair_Scheduling_Input_Buffered_Crossbar_Switch.ps.gz.
                                          47. Markatos, E.P. (2001). Speeding up TCP / IP : Faster Processors are not Enough. 2001.TR297.SpeedingUp_TCP_IP_faster_processors.ps.gz.
                                          48. Markatos, E.P. (2001). Tracing a large-scale Peer to Peer System: an hour in the life of Gnutella. 2001.TR298.Tracing_Peer_to_Peer_System.ps.gz.
                                          49. Ioannou, A. (2000). An ASIC Core for Pipelined Heap Management to Support Scheduling in High Speed Networks. 2000.TR278.ASIC_Core_Pipelined_Heap_High_Speed_Networks.ps.gz.
                                          50. Markatos, E.P., Pnevmatikatos, D., Flouris, M.D., & Katevenis, M.G.H. (2000). Web-Conscious Storage Management for Web Proxies. 2000.TR275.Web-Conscious_Storage_Management_Web-Proxies.ps.gz.
                                          51. Katehakis, D.G., Chalkiadakis, G., Tsiknakis, M.N., & Orphanoudakis, S.C. (1999). A distributed, agent-based architecture for the acquisition, management, archiving and display of real-time monitoring data in the intensive care unit.. 1999.TR261.Intensive-Care_CORBA_SoftwareAgents_real-time-ICU-monitoring.ps.gz.
                                          52. Dollas, A., Papadimitriou, K., Mathioudakis, C., Markatos, E.P., & Katevenis, M.G.H. (1999). Experimental ATM Network Interface Performance Evaluation. 1999.TR244.ATM_if_perf.ps.gz.
                                          53. Mavroidis, I. (1999). Hardware Implementation of a Routine Filter to support Wormhole IP over ATM. 1999.TR258.RoutingFilterCore.ps.gz.
                                          54. Sapountzis, G. (1999). Routing Table Organization and Management in the Wormhole IP Routing Filter. 1999.TR257.RTOrgMng.ps.gz.
                                          55. Markatos, E.P. (1998). A Cash-based Approach to Caching Web Documents. 1998.TR230.cash_based_caching.ps.gz.
                                          56. Katevenis, M.G.H., Serpanos, D.N., & Spyridakis, E. (1998). Credit-Flow-Controlled ATM for MP Interconnection: the ATLAS I Single-Chip ATM Switch. 1998.HPCA.atlas4mp.ps.gz.
                                          57. Glykopoulos, G. (1998). Design and Implementation of a 1.2 Gbit/s ATM Cell Buffer using a Synchronous DRAM chip. 1998.TR221.ATM_Cell_Buffer_using_SDRAM.ps.gz.
                                          58. Mavroidis, I. (1998). Heap Management in Hardware. 1998.TR222.Heap_Management_in_Hardware.ps.gz.
                                          59. Kornaros, G., Pnevmatikatos, D., Vatsolaki, P., Kalokairinos, G., Xanthaki, Ch., Mavroidis, D., Serpanos, D.N., & Katevenis, M.G.H. (1998). Implementation of ATLAS I: a Single-Chip ATM Switch with Backpressure. 1998.HOTI.atlasIimpl.ps.gz.
                                          60. Papathanasiou, A E., & Markatos, E.P. (1998). Lightweight Transactions on Networks of Workstations. 1998.ICDCS.ps.gz.
                                          61. Ioannidis, S., Markatos, E.P., & Sevaslidou, J.E. (1998). On Using Network Memory to Improve the Performance of Transaction -Based Systems. 1998.PDTA.RVM_EXODUS.ps.gz.
                                          62. Pnevmatikatos, D., Markatos, E.P., Magklis, G.I., & Ioannidis, S. (1998). On Using Network RAM as a non-volatile Buffer. 1998.TR227.NVRAM.ps.gz.
                                          63. Flouris, M.D., & Markatos, E.P. (1998). The Network RamDisk : Using Remote Memory on Heterogeneous NOWs. 1998.TR226.nrd_TR.ps.gz.
                                          64. Markatos, E.P., Katevenis, M.G.H., & Vatsolaki, P. (1998). The Remote Enqueue Operation on Networks of Workstations. 1998.CANPC98.REQ.ps.gz.
                                          65. Katevenis, M.G.H., Vatsolaki, P., Serpanos, D.N., & Markatos, E.P. (1997). ATLAS I: A Single-chip ATM switch for NOWs. 1997.CANPC97.ATLAS.ps.gz.
                                          66. Katevenis, M.G.H. (1997). Buffer Requirements of Credit-Based Flow Control when a Minimum Draining Rate is Guaranteed. 1997.HPCS97.drain_cr_buf.ps.gz.
                                          67. Markatos, E.P., Katevenis, M.G.H., Kalokairinos, G., Magklis, G.I., Milolidakis, G., & Oikonomou, Th. (1997). Issues in the Design and Implementation of User-Level DMA. 1997.TR182.UDMA.ps.gz.
                                          68. Papathanasiou, A E., & Markatos, E.P. (1997). Lightweight Transactions on Networks of Workstations. 1997.TR209.Lightweight_Transactions_on_NOWs.ps.gz.
                                          69. Katevenis, M.G.H., Serpanos, D.N., & Markatos, E.P. (1997). Multi-Queue Management and Scheduling for Improved QoS in Communication Networks. 1997.EMMSEC.Muqpro.ps.gz.
                                          70. Ioannidis, S., Markatos, E.P., & Sevaslidou, J.E. (1997). On using Network Memory to Improve the Performance of Transaction-Based Systems. 1997.TR190.Remote_memory_RVM.ps.gz.
                                          71. Kornaros, G., Kozyrakis, Ch., Vatsolaki, P., & Katevenis, M.G.H. (1997). Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control. 1997.ARVLSI.Pipe_MultiQueue.ps.gz.
                                          72. Artavanis, M. (1997). Simulation of the Shared Disks Architecture for Transaction Processing Systems. 1997.TR211.Simulation_SharedDisks_Archit_Transaction_Processing_Systems.ps.gz.
                                          73. Katevenis, M.G.H., Serpanos, D.N., & Spyridakis, E. (1997). Switching Fabrics with Internal Backpressure using the ATLAS I Single-Chip ATM Switch. 1997.GLOBECOM.ATLAS_I_Fabrics.ps.gz.
                                          74. Markatos, E.P., & Katevenis, M.G.H. (1997). User-Level DMA without Operating System Kernel Modification. 1997.HPCA97.user_level_dma.ps.gz.
                                          75. Markatos, E.P. (1997). Visualizing Working Sets. 1997.TR192.Visualizing_working_sets.ps.gz.
                                          76. Markatos, E.P., & Chronaki, C. (1996). A Top-10 Approach to Prefetching on the Web. 1996.TR173.Web_Prefetching.ps.gz.
                                          77. Nikolaou, Ch., Markatos, E.P., Karavassili, M., & Saridakis, T. (1996). ArrayTracer: A Parallel Performance Analysis Tool. 1996.TR162.ArrayTracer_A_Parallel_Performance_Analysis_Tool.ps.gz.
                                          78. Katevenis, M.G.H., Serpanos, D.N., & Vatsolaki, P. (1996). ATLAS I: A General-Purpose, Single-Chip ATM Switch with Credit-Based Flow Control. 1996.HOTI.ATLAS_I_ATMswitchChip.ps.gz.
                                          79. Katevenis, M.G.H., & Vatsolaki, P. (1996). ATLAS I: A Single-Chip ATM Switch with HIC Links and Multi-Lane Back-Pressure. 1996.EMSYS96.ATLAS_I_ATMswitchHIC.ps.gz.
                                          80. Spyridakis, E. (1996). Comparison of Credit Based ATM and Wormhole Under Bursty Traffic or With Hot Spots. 1996.TR170.ATM_vs_Wormhole_in_Greek.ps.gz.
                                          81. Katevenis, M.G.H., Vatsolaki, P., & Chalkiadakis, V. (1996). Credit-Flow-Controlled ATM over HIC Links in the ASICCOM ''ATLAS I"" Single-Chip Switch. 1996.RTMagazine.ATLAS_I_ATMswitchChip.ps.gz.
                                          82. Katevenis, M.G.H., Serpanos, D.N., & Spyridakis, E. (1996). Credit-Flow-Controlled ATM versus Wormhole Routing. 1996.TR171.ATM_vs_Wormhole.ps.gz.
                                          83. Markatos, E.P., & Dramitinos, G. (1996). Implementation of a Reliable Remote Memory Pager. 1996.usenix.ps.gz.
                                          84. Markatos, E.P. (1996). Issues in Reliable Network Memory Paging. 1996.MASCOTS96.Reliable_Network_Memory.ps.gz.
                                          85. Markatos, E.P., & Katevenis, M.G.H. (1996). Telegraphos :High-Performance Networking for Parallel Processing on Workstation Clusters.. 1996.HPCA96.Telegraphos.ps.gz.
                                          86. Kozyrakis, Ch. (1996). The Architecture, Operation, and Design of the Queue Management Block in the ATLAS I ATM Switch. 1996.TR172.QueueManagement.ps.gz.
                                          87. Markatos, E.P. (1996). Using Remote Memory to avoid Disk Thrashing: A Simulation Study. 1996.MASCOTS96.Remote_memory_paging.ps.gz.
                                          88. Efthymiou, A. (1995). Design, Implementation, and Testing of a 25 Gb/s Pipelined Memory Switch Buffer in Full-custom CMOS. 1995.TR143.Design_Implementation_25Gbs_PipelinedMem_Switch_Buffer.ps.gz.
                                          89. Markatos, E.P., Dramitinos, G., & Papachristos, K. (1995). Implementation and Evaluation of a Remote Memory Pager. 1995.TR129.remote_memory_paging.ps.gz.
                                          90. Labrinidis, A. (1995). Methods to cluster transactions into utilization classes with similar workload characteristics. 1995.TR135.Methods_cluster_transactions_similar_workload_characteristics.ps.gz.
                                          91. Katevenis, M.G.H., Vatsolaki, P., & Efthymiou, A. (1995). Pipelined Memory Shared Buffer for VLSI Switches. 1995.SIGCOMM95.PipeMemoryShBuf.ps.gz.
                                          92. Katevenis, M.G.H., Vatsolaki, P., Efthymiou, A., & Stratakis, M. (1995). VC-level Flow Control and Shared Buffering in the Telegraphos Switch. 1995.HOTI.VCflowCtrlTeleSwitch.ps.gz.
                                          93. Xanthaki, Z. (1994). A Memory Controller for Access Interleaving over a single Rambus. 1994.TR124.RAMBUS_AccessInterleaving_MemoryController.ps.gz.
                                          94. Chatzaki, M. (1994). A Translation Scheme Between Two Real-Time Formalisms. 1994.TR128.specification_automatic_verification_timed_automata.ps.gz.
                                          95. Dimitriadis, G. (1994). An Arithmetic Entropy Codec VLSI chip for JPEG Image Compression. 1994.TR114.Arithmetic_Entropy_Codec_VLSI_chip_for_JPEG.ps.gz.
                                          96. Katevenis, M.G.H. (1994). FORTH, ICS: Computer Architecture and VLSI Systems Group: A Profile. 1994.AVG_PROFILE.ps.Z.
                                          97. Katevenis, M.G.H., Vatsolaki, P., & Efthymiou, A. (1994). Pipelined Memory Organization for High Performance Switching and Buffering. 1994.TR127.PipelinedMemory.ps.Z.
                                          98. Katevenis, M.G.H. (1994). Telegraphos: High-Speed Communication Architecture for Parallel and Distributed Computer Systems. 1994.TR123.Telegraphos.ps.Z.
                                          99. Markatos, E.P., & Chronaki, C. (1994). Using reference counters in Update Based Coherent Memory. 1994.PARLE94.Reference_Counters.ps.Z.
                                          100. Markatos, E.P. (1993). How Architecture Evolution Influences the Scheduling Discipline used in Shared-Memory Multiprocessors. 1993.PARCO93.Architecture_infuence_on_Scheduling.ps.Z.
                                          101. Markatos, E.P., & Leblanc, Th.J. (1993). Locality-Based Scheduling in Shared-Memory Multiprocessors. 1993.TR94.Locality_Based_Scheduling.ps.Z.
                                          102. Markatos, E.P., & Chronaki, C. (1993). Trace-Driven Simulation of Data-Alignment and other Factors affecting Update and Invalidate Based Coherent Memory. 1993.TR93.DATA_ALIGNMENT_IN_VIRTUAL_SHARED_MEMORY.ps.Z.
                                          103. Markatos, E.P., & LeBlanc, T.J. (1993). Using Processor Affinity in Loop Scheduling on Shared-Memory Multiprocessors. 1993.TPDS.Affinity_Loop_Scheduling.ps.Z.
                                          104. Vatsolaki, P. (1992). Design of a High-Speed UART VLSI Library Cell. 1992.TR50.High_Speed_UART_VLSIlibCell.ps.Z.
                                          105. Sidiropoulos, S. (1991). A General Purpose ATM Switch Chip : Architecture and Feasibility Study. 1991.TR025_General_Purpose_ATM_Switch_Chip.pdf.
                                          106. Sidiropoulos, S. (1991). Fast Packet Switches for Asynchronous Transfer Mode. 1991.TR25.Fast_packet_switches.ps.Z.
                                          107. Katevenis, M.G.H. (1987). Fast Switching and Fair Control of Congested Flow in Broad-Band Networks. 1987.TR001_Fast-Switching_Fair-Control_Broad-Band-Networks.pdf.
                                            M.S. Theses

                                          1. Stavrakantonaki, E. (2016). A static pointer analysis on intermediate representation for compilation optimizations
                                          2. Vasilakis, E. (2015). An Instruction Level Energy Characterization of ARM Processors
                                          3. Papakonstantinou, N. (2015). Combining Recursively Parallel Runtimes with Blocked-based Dependence Analysis
                                          4. Papoulas, C. (2015). Design and Implementation of a Social Networking Architecture for Cloud Deployment Specialists
                                          5. Glenis, A. (2015). FT-Myrmics : A fault tolerant runtime system for task based programming models
                                          6. Papagiannis, A. (2013). Implementing Scalable Parallel Programming Models with Hybrid Address Spaces
                                          7. Stamatakis, D. (2012). Scalability of Replicated Metadata Services in Distributed File Systems
                                          8. Chasapis, K. (2012). Bladefs: Design and Implementation of a kernel level file system for scalable storage servers
                                          9. Papatriantafyllou, A. (2012). Efficient and Accurate Block-Level Dependence Analysis For Task Dataflow Models
                                          10. Zakkak, F. S. (2012). SCOOP: Language extensions and compiler optimizations for task-based programming models
                                          11. Klonatos, I. (2011).  Design and Evaluation of Solid-State Drive (SSD) Caches to Improve Storage I/O Performance. University of Crete.
                                          12. Tsaliagkos, D. (2011). Design and Implementation of a Directory based Cache Coherence Protocol
                                          13. Saloustros, G. (2011). Design and Implementation of a Scalable Storage System for Fully-Consistent Replicated Data Logging
                                          14. Kesapidis, I. (2011). Dynamic Dependence Analysis on Multi-core Processors
                                          15. Fountoulakis, M. (2010). DARC: Design and Evaluation of an I/O Controlller for data Protection. May 2010.
                                          16. Alvanos, M. (2010). Design and Evaluation of a Task -based Paraller H.264 Video Encoder for the Cell Processor. July 2010.
                                          17. Koukos, K. (2010). Locality management in task-based parallel programming models. August 2010.
                                          18. Zampetakis, M. (2010). Runtime support for programming explicit communication chip multiprocessors. July 2010.
                                          19. Sempepou, Z. (2010). Scalable storage support and fault-tolerance for data stream processing systems. July 2010.
                                          20. Katsamali, M. (2010). Software implementation of MPI primitives in multicore FPGA. June 2010.
                                          21. Makatos, A. (2010). ZBD: Using Transparent Compression at the Block Level to Increase Storage Space Efficiency. March 2010.
                                          22. Nikiforos, G. (2009). FPGA implementation of a cache controller with configurable scratchpad space. April 2009.
                                          23. Tzenakis, G. (2009). Tagged Procedure Calls (TPC): Efficient runtime support for task-based parallelism on the Cell Processor. November 2009.
                                          24. Kasapaki, E. (2008). An EDA Tool for the Timing Analysis, Optimization and Timing Validation of Asynchronous Circuits. 2008.
                                          25. Passas, S. (2008). Analysis and Optimization of Overheads in Communication Protocols Over High Speed Ethernet-based Cluster Interconnects. April 2008.
                                          26. Mangas, E. (2008). Fine-grained Localization in Wireless Sensor Networks using Acoustic Sound Transmissions and High Precision Clock Synchronization. December 2008.
                                          27. Aslanidis, I. (2008). Multi-valued logic synthesis. April 2008.
                                          28. Pantelias, E. (2008). Αποσυγχρονισμός Βιομηχανικών Κυκλωμάτων. April 2008.
                                          29. Michelogiannakis, G. (2007). Approaching Ideal NoC Latency with Pre-Configured Routes. September 2007.
                                          30. Matthaiakis, P. (2007). Gated Dual-Rail - A Methodology for Reducing the Power Consumption of Monotonic Dual-Rail Circuits. December 2007.
                                          31. Papamichail, M. (2007). Network Interface Architecture and Prototyping for Chip and Cluster Multiprocessors. September 2007.
                                          32. Andrikos, N. (2006). A Fully-Automated Desynchronization Flow for Synchronous Circuits. April 2006.
                                          33. Vlachos, E. (2006). Design and Implementation of a Coherent Memory Sub-System for Shared Memory Multiprocessors. April 2006.
                                          34. Kotsis, G. (2006). Improving Scalability on Shared Memory Clusters. December 2006.
                                          35. Passas, G. (2006). Packet Mode Scheduling in Buffered Crossbar Switches. April 2006.
                                          36. Panagiotakis, G. (2006). Reducing Disk I/O Performance Sensitivity for Large Numbers of Sequential Streams. September 2006.
                                          37. Giannakopoulos, I. (2005). CORMOS: A Communication-Oriented Runtime System for Wireless Sensor Networks. April 2005.
                                          38. Papaefstathiou, V. (2005). Design and Implementation of Network Packet Classification Engines. April 2005.
                                          39. Dokianaki, O. (2005). Evaluation of Asynchronous Interconnect Techniques for Digital SoC. April 2005.
                                          40. Xynidis, D. (2005). Performance Analysis and Scaling of Networked Shared Block-Level Storage. December 2005.
                                          41. Kounalakis, E. (2005). The Mythical IP Block: An Investigation of Contemporary IP Characteristics. December 2005.
                                          42. Simos, D.G. (2004). Design of a 32x32 Variable Packet-Size Buffered Crossbar Switch Chip. November 2004.
                                          43. Xynidis, K. (2004). Network Intrusion Prevention on Multilevel Processing Architectures. November 2004.
                                          44. Sarmpanis, A. (2004). Ένα Πρωτόκολλο Εκμισθώσεων για την Ενημέρωση Δεδομένων Προσωρινών Μνημών peer-to-peer δικτύων. November 2004.
                                          45. Charitakis, I. (2004). Εφαρμογές του Επεξεργαστή Δικτύων IXP 1200 σε Συστήματα Ανίχνευσης Εισβολέων για Δίκτυα. April 2004.
                                          46. Papachristos, Ch. (2002).  Navigation Technologies over low bandwidth links for Thin Clients An introduction to the CC/PP protocol. December 2002.
                                          47. Kapsalis, D. (2002). Design and Implementation of a per-Flow Queue Manager of an ATM Switch using FPGA Technology. March 2002.
                                          48. Charteros, K. (2002). Fast Parallel Comparison Circuis for Scheduling. March 2002.
                                          49. MeÃntanis, D. (2002). Hardware Conversion and Software Import to a Prototype Microprocessor Board. December 2002.
                                          50. Kalyvianaki, E. (2002). Î§-PacketQ a network tragic visualization tool. A reial-time approach for multiple users. December 2002.
                                          51. Lymperis, S. (2002). Implementation of a Motion Compensaation Subsystem for an MPEG-II Decoder. December 2002.
                                          52. Chrysos, N. (2002). Weighted Max-Min Fair Scheduling, for a Crossbar, with Small Internal Memory. 2002.
                                          53. Sapountzis, G. (2002). Πλέγματα Μεταγωγής BENES με Εσωτερικό Backpressure Πολυπλοκότητας O(N). December 2002.
                                          54. Papadakis, G. (2001). Design and FPGA Implementation of an ABR traffic scheduler and utopia interfaces for an ATM network switch. November 2001.
                                          55. Gialama, A. (2001). Distributed Video Server with Quality of Service. June 2001.
                                          56. Asimakopoulou, X.A. (2001). Effective Resource Discovery on the World Wide Web. June 2001.
                                          57. Danalis, A. (2001). Firewall development for the embedded network processor IXP1200. July 2001 .
                                          58. Lolas, Ch. (2001). Low Level Software Design and Implementation for High Performance Packet Switches. November 2001.
                                          59. Ioannou, A. (2000). An ASIC Core for Pipelining Heap Management to Support Scheduling in High Speed Networks. November 2000.
                                          60. Oikonomou, A. (2000). Architecture and Implementation of an Adaptation Bridge for ATM Networks. June 2000.
                                          61. Flouris, M.D. (2000). Design & Implementation of Methods Enchancing the Performance of www Proxies. March 2000.
                                          62. Nikologiannis, A. (2000). Efficient Per-Flow Queuing in DRAM at OC-192 Line Rate using Out-of-Order Execution Techniques. November 2000.
                                          63. Sidiropoulos, A. (1999). Distributed Indexing and Searching Mechanisms. March 1999.
                                          64. Chatzistamatiou, A. (1999). EasyAgent: a Masif Compliant Environment for Mobile Java Objects. March 1999.
                                          65. Papathanasiou, A E. (1999). Effective Resource Discovery on the World Wide Web. June 1999.
                                          66. Milolidakis, G. (1999). MemSpyer: A Performance Debugging Tool which simulates and visualizes memory hierarchy. March 1999.
                                          67. Glykopoulos, G. (1998). Design and Ιmplementation of an 1.2 Gbit/s ATM Cell Buffer using a Synchronous DRAM chip. July 1998.
                                          68. Karakonstantis, P. (1998). Efficient Memory Management for high-speed ATM networks. November 1998.
                                          69. Kornaros, G. (1997).  Implementation of Pipelined Multi- Queue Management in the ATLAS I Switch in Full- Custom CMOS VLSI. June 1997.
                                          70. Zarras, A. (1997). Array Tracer : Parallel Performance Analysis and Visualization. March 1997.
                                          71. Gkanas, L. (1997). New Caching ways in the World Wide Web. 1997.
                                          72. Terzis, S. (1997). Performance Monitoring in Digital Library Systems. November 1997.
                                          73. Artavanis, M. (1997). Simulation of the Shared Discks Architecture for Transaction Processing Systems. November 1997.
                                          74. Moraiti, M. (1997). Trace-driven Simulation of ATM and Wormhole networks. November 1997.
                                          75. Anastasiadi, A. (1996).  A study of Microeconomic Algorithms for Load Balancing and Data Replication in Distributed Computer Systems. November 1996.
                                          76. Spyridakis, E. (1996). Comparative Study of Credit Flow Controled ATM and Wormhole Networks Under Bursty Traffic and Witg Hot Spots. 1996.
                                          77. Papachristos, K. (1996). Design and Implementation of the Telegraphos Operations for the Mach Operating System. March 1996.
                                          78. Dramitinos, G. (1996). Reliable Paging to Remote Main Memory in a Workstation Cluster. 1996.
                                          79. Ioannidis, S. (1996). Using the Remote Main Memory in a Workstation Cluster for Reliability and Performance in Transactional Based Systems. November 1996.
                                          80. Sareidakis, T. (1995). Array Tracer: A Parallel Performance Analysis Tool. November 1995.
                                          81. Efthymiou, A. (1995). Design of a 25 Gbits/sec Pipelined Menory for Shared Buffer Network Switches. November 1995.
                                          82. Marazakis, M. (1995). Simulation and Transaction Processing Systems and A Study of Methods for Performance Goal Satisfaction. November 1995.
                                          83. Lamprinidis, A. (1995). Μέθοδοι Ταξινόμησης Δοσοληψιών σε Ομάδες με Παρόμοια Χαρακτηριστικά Φόρτου Εργασίας. November 1995.
                                          84. Karavasili, M. (1994). An Algorithm to Layout Directed Graphs. March 1994.
                                          85. Dimitriadis, G. (1994). An Arithmetic Entropy Codec VLSI chip for JPEG compression. March 1994.
                                          86. Xanthaki, Z. (1994). Ενας Ελεγκτής για Διαφύλλωση Προσπελάσεων σε ένα Απλό Rambus. March 1994.
                                          87. Farsaris, I. (1993). Design and Implementation of undo-redo mechanism in Labyrinth System. May 1993.
                                          88. Karydis, N. (1993). Βιβλιοθήκη Γεωμετρικών Κυττάρων και Μετασχηματισμών για τον Λαβύρινθο. April 1993.
                                          89. Moschovos, A. (1992). Implementing non-numerical algorithms on a decoupled architecture supporting software pipelining.  (pdf in english) (pdf in greek).
                                          90. Kalogerakis, P. (1992). Ο Μηχανισμός Υπολογισμού Κυττάρων στο Λαβύρινθο. September 1992.
                                          91. Sorilos, A. (1992). Οντοκεντρικός Σχεδιασμός Γραφικών στο Σύστημα Λαβύρινθος. September 1992.
                                          92. Vatsolaki, P. (1992). Σχεδίαση Ενός Υψηλής Ταχύτητας UART Δομικού Στοιχείου για Βιβλιοθήκες Ολοκληρωμένων Κυκλωμάτων VLSI. 1992.
                                          93. Georgis, Ch. (1992). Σχεδιασμός και Υλοποίηση του Γραφικού Τμήματος του Λαβυρίνθου. March 1992.
                                          94. Sidiropoulos, S. (1991). A General Purpose ATM Switch Chip: Architecture and Feasibility Study. September 1991.
                                          95. Tzartzanis, N. (1991). Αναδιάταξη Κώδικα σε Μνήμη Διπλού Πλάτους για Ελάττωση του Κόστους των Διακλαδώσεων. June 1991.
                                          96. Chalkiadakis, V. (1990). Αρχική Σχεδίαση και Υλοποίηση του Ring 64: Δίκτυο Τοπολογίας Δακτυλίου για Πακέτα Δεδομένων και Φωνής με Ταχύτητα Μεγαλύτερη από 64 Mb/s. December 1990.
                                            Ph.D. Theses

                                          1. Lyberis, S. (2013). Myrmics: a scalable runtime system for global address spaces
                                          2. Passas, G. (2012). VLSI Micro-Architectures for High-Radix Crossbars
                                          3. Kavadias, S.G. (2010). Direct Communication and Synchronization Mechanisms in Chip Multiprocessors
                                          4. Chrysos, N. (2007). Request- Grant Scheduling for Congestion Elimination in Multistage Networks. May 2007.
                                          5. Marazakis, E. (2000). Service Composition and Service- level Agreements in Open Distributed Systems. December 2000.
                                            Other Technical Reports

                                          1. Faith, E., Fatourou, P., Kosmas, E., Milani, A., & Travers, C. (2012). Universal Constructions that Ensure Disjoint-Access Parallelism and Wait-Freedom

                                            Others (2)

                                                  Miscellaneous

                                                1. Chaix, F., & Fujiwara, I. , Koibuchi, M.  (2015). Evaluation of applications performance for different supercomputers network topologies. Poster presentation and short paper at the ACACES Summer School (HiPEAC). Fiuggi, Italy, July .
                                                2. Hessel, F., Kent, K.B., & Pnevmatikatos, D. (2008). Editorial: Embedded systems - new challenges and future directions. ACM Trans.Embedded Comput.Syst., 7 (4).
                                                    Found: 620 publications
                                                    © Copyright 2007 FOUNDATION FOR RESEARCH & TECHNOLOGY - HELLAS, All rights reserved.