CARV Laboratory

As the core count rises in modern multicore processors, scalability, performance, and energy consumption issues lead hardware manufacturers towards non cache coherent architectures. High-productivity languages like Java cannot currently take advantage of such architectures because they rely on cache coherence. This project proposes a power-efficient Java Runtime Environment for non cache coherent architectures, and takes a significant step towards simplifying and improving the programmability of future multicore computing systems in general. It contributes to increasing the variety of computing platforms on which Java-coded applications may run and makes virtualization even more efficient. Thus, this work goes beyond on-chip, off-chip boundaries for large-scale, heterogeneous, multicore parallel systems.

Java has a profound impact on the computing world. It is a portable, high-productivity language, used by a plethora of cross-cutting technologies that are applicable to several different market segments of computing systems. Ranging from embedded systems, car computers and cellphone software like Android, to personal computing and network applications, and up to large-scale datacenter and supercomputing applications like Hadoop and Google’s map-reduce framework, Java is ubiquitous in the IT industry. Thus, an energy-efficient Java Virtual Machine that scales to upcoming multicore and manycore architectures will impact the performance of existing systems, facilitate development and production of future applications, and thus significantly shorten the time-to-market for several emerging technologies and products.

It is a common belief that “For the foreseeable future, concurrent data structures will lie at the heart of multicore applications, and the larger our library of scalable concurrent data structures, the better we can exploit the promise of multicore architectures” (M. Herlihy, CACM 2009). By developing a comprehensive library of concurrent data structures and algorithms, this project will advance the state of the art towards easier, more power efficient and scalable concurrent computing.

The power consumption of multicore processors is nowadays considered as one of their most important characteristics. Our goal to develop techniques and tools for measuring power consumption is a necessary step for the production of more power-efficient hardware and software. Moreover, it advances the state of the art beyond existing, intra-core, power-consumption estimation techniques, by targeting novel, scalable multicore architectures in which inter-core communication and memory become much more significant factors for power consumption. Finally, architectural support for power-consumption estimation in manycore processors unravels a new field of research in adaptable software that can optimize for power efficiency, communication or peak-performance.