Ioannis Papaefstathiou

Addresses

Work University of Crete Computer Science Department P.O.Box 2208, Heraklion, Crete, GR-714 09 GREECE Tel: (+30)81 391663

Home Stergohianni 18 Heraklion, Crete, GR-71205 GREECE E-mail : ygp@csd.uch.gr Tel: (+30)81 312649

Personal information

Date of birth: 3rd September, 1974. Citizenship: Greek.

Research Interests

I am interested in the architecture and design of novel computer systems, focusing mostly on media and network processing devices and the interaction between VLSI and computer architecture. Currently I concentrate on the design and implementation of specific purpose microprocessors with tightly coupled design parameters and highly constrained resources such as network processors. Successful designs in this area require optimization in both hardware and software and they integrate ideas from computer networking with ideas from system design and computer architecture. I am also interested in high-speed systems for encryption, compression or any other data manipulation method.

Education 10/1997-08/2000 09/1996-06/1997 09/1992-06/1995

Cambridge University, Fitzwilliam College, UK Ph.D. Degree in Computer Science, Research Advisor: Professor Ian Leslie. Thesis: Accelerating high speed networks using compression. Harvard University, USA. M.Sc. Degree in Computer Science, Major: Computer Systems. GPA: A (Maximum Grade is A) Class Ranking : 1st (in the history of the master). University of Crete, Greece. B.Sc. Degree in Computer Science, Area of Specialization: Computer Architecture and Digital Systems. GPA: 8.87 (out of 10), Excellent. Class Ranking : 2nd (out of 74).

Special awards

Marie Curie Research Fellowship, TMR Activity 3, EU, 1998-2000. Graduated in Computer Science in 3 years (4 is normal). Scholarship by the Greek Foundation of Research and Technology, 1995. Scholarship by the Greek National Scholarships Foundation, 1993-5. Award by the Greek Mathematics Society, May 1991, May 1989.

Professional Experience 09/2001- present 01/2002- present 09/2000-08/2001 10/1997-07/2000 07/1995-07/1996 09/1994-06/1995

Visiting Assistant Professor-Researcher, University of Crete, Greece and Foundation of Research and Technology, Hellas. Teaching undergraduate and graduate courses: "EDA design for Digital VLSI Systems", "Digital Circuits Lab", "Microprocessors, Microcontrollers and Peripherals", "Computer Architecture", “Advanced Computer Architecture”. Supervising 2 M.Sc. Students and 2 B.Sc. students. Doing research on Home Area Networks (HANs) and Network Processors. Hardware Design Consultant, Ellemedia Technologies, Greece. Working in the Architectural Design and Implementation of various Network Devices the Company produces and especially in a state-of-the-art multi-Gigabit Network Processor. Business Analyst-Software Developer, KBC Financial Products (former D.E.Shaw) London, UK. Part of an International Team of 15 Developers and Analysts I analyzed the requirements for amendments to the existing Trading/Reporting System and developed the code for implementing them. Also I Designed and Developed a new Tool for monitoring the Risk Exposure of the company and I was the sole analyst/designer of a new sophisticated tool for calculating the values of certain types of derivatives (for listed options). Research Assistant, Systems Research Group, Computer Laboratory, University of Cambridge, UK. Sole designer of a complete hardware prototype for on-line compression of network streams and developer of the software running on it. Systems Engineer, Computer Architecture and VLSI Systems Design Group, Institute of Computer Science, FORTH, Greece. Part of a group of 14 engineers and computer scientists, I designed certain circuits for ATLAS single chip network switch, and developed the high-level model for testing it, within the ASICCOM project. Trainee Systems Engineer, Computer Architecture and VLSI Systems Design Group, Institute of Computer Science, FORTH, Greece. Part of a group of 8 engineers and computer scientists, I developed the software needed for transferring data to and from the Telegraphos II single chip switch, within the Telegraphos project.

Additional Teaching Experience

Regularly performed supervision duties over a wide range of applied computer science subjects for a plethora of Cambridge colleges. Co-taught a twenty lecture course on "VLSI Systems Design" to postgraduate students at Harvard University. Delivered lectures on related topics. Taught three sixteen lecture courses to undergraduate students at North College, Greece.

Technical Skills

Hardware Design Tools Fluent in Verilog-XL, excellent knowledge of Synopsys, Synplify, Cadence’s Silicon Ensemble and Silicon Encounter, Xilinx’s Alliance and Foundation. Very good knowledge of VHDL, Hspice and Ranger. Software Design Tools Excellent knowledge in C, Java, embedded-SQL, Tcl/Tk and Pascal, good knowledge of Visual C++, Fortran and Perl.

Publications & Presentations

Patent Granted "ATM Compression Scheme", UK Patent Num : GB2350028 Journal Papers I. Papaefstathiou, S. Perissakis, T. Orphanoudakis, N. Nikolaou, G. Kornaros, , D. Pnevmatikatos, G. Konstantoulakis, N. Zervos “A State-of-the-art Network Processor for Multi-Gigabit networks”, to appear IEEE Micro, special Issue on Network Processors, Sep/Oct 2004. I. Papaefstathiou, “Titan II : An IPComp Processor for 10Gbit/sec network”, accepted for publication in IEEE Design & Test (D&T). I. Papaefstathiou, G. Kornaros, N. Chrisos, “A Buffered Crossbar-Based NoC with Multi-Priority Support ”, accepted for publication in Elsevier Journal of Systems Architecture (JSA). I. Papaefstathiou, K. Vlachos, N. Nikolaou and V.B. Lawrence, “Packet processing acceleration with a 3-stage re-configurable pipeline engine”, IEEE Communications Letters, Volume: 8,   Issue: 3,   March 2004. Ι. Papaefstathiou, V. Papaefstathiou and C. Sotiriou, “Design-Space Exploration of the most widely used Cryptography Algorithms”, accepted for publication in Elsevier Journal on Microprocessors and Microsystems, special issue on Secure Computing Platforms A. Nikologiannis, I. Papaefstathiou, G.Kornaros, C. Kachris, “An FPGA-based Queue Management System for High Speed Networking Devices”, Elsevier Journal on "Microprocessors and Microsystems", special issue on FPGAs, Volume 28, Issues 5-6 , 2 August 2004, Pages 223-236. I. Papaefstathiou, “Low level Hardware Compression for Multi-Gigabit Networks”, accepted for publication in Journal of Circuits, Systems and Computers, special issue on VLSI Architectures for Multimedia Applications. I. Papaefstathiou, C. Manifavas, “Evaluation of Micropayment Transaction Cost”, Journal of Electronic Commerce Research, Volume : 5, Number : 2, 2004, Pages 99-114. Conference Papers I. Papaefstathiou, G. Kornaros, “Software processing performance in network processors”, 2004 IEEE Design Automation & Test in Europe (DATE 2004), February 16-20, Paris, France. Manolis Katevenis, Georgios Passas, Dimitrios Simos, Ioannis Papaefstathiou & Nikos Chrysos, “Variable Packet Size Buffered Crossbar (CICQ) Switches”, 2004 IEEE International Conference on Communications (ICC 2004), June 20-24, Paris, France. I. Papaefstathiou, “Performance against cost trade-offs for Hardware Compression in 10 Gigabit Networks”, to appear in 10^th IEEE International Conference on Electronics, Circuits and Systems, (ICECS2003) , December 14 - 17, 2003, Sharja, U.A.E. C. Sotiriou, I. Papaefstathiou, “A Design-Space Exploration of Alternative DES Implementations”, 10^th IEEE International Conference on Electronics, Circuits and Systems, (ICECS2003) , December 14 - 17, 2003, Sharja, U.A.E. N. Mouratidis, G. Lykakis, A. Tavoularis, A. Kostopoulos, F. Petreas, D. Economou, A. Manousaridis, V. Vlaggoulis1, Y. Papaefstathiou, Ch. Georgopoulos, G. Konstantoulakis, “Convergence Processor: Standard and Custom IP in an Innovative SoC Design for Broadband Residential Applications”, IIIS International Conference on Computer, Communication and Control Technologies (CCCT’03), July 31, August 1-2, 2003, Orlando, Florida, U.S.A. , Best paper award G. Kornaros, I. Papaefstathiou, “ An Innovative Resource Management Scheme for Multi-Gigabit Networking Systems”, 6th IEEE International Conference on High Speed Networks and Multimedia Communications (HSNMC'03), July 23-25, 2003 Estoril, Portugal. G. Kornaros, T. Orphanoudakis, I.Papaefstathiou,” GFS: An Efficient Implementation of Fair Scheduling for multi-Gigabit Packet Networks”, 14th International Conference on Application-specific Systems, Architectures and Processors (ASAP 2003), June 24-26, 2003, Hague, The Netherlands. G. Kornaros, I. Papaefstathiou, A. Nikologiannis, N.Zervos, “A Fully-Programmable Memory Management System Optimizing Queue Handling at Multi Gigabit rates”, 40th IEEE/ACM Design Automation Conference (DAC), June 2-6, 2003, Anaheim, California, U.S.A., G. Kornaros, T. Orphanoudakis, I. Papaefstathiou, “ Active Flow Identifiers for scalable, QoS scheduling in 10-Gbps network processors”, 2003 IEEE International Symposium on Circuits and Systems (ISCAS 2003), May 25 - 28, 2003, Bangkok, Thailand. I. Papaefstathiou, H.-C. Leligou, Th. Orphanoudakis, G. Kornaros, N. Zervos, G. Konstantoulakis, “An innovative scheduling scheme for high speed network processors”, IEEE International Symposium on Circuits and Systems (ISCAS 2003), May 25 - 28, 2003, Bangkok, Thailand. T. Orphanoudakis, G. Kornaros, H.-C. Leligou, I. Papaefstathiou, S. Perissakis, N.Zervos, “Scheduling components for multi-gigabit network SoCs”, 2003 SPIE First International Symposium on Microtechnologies for the New Millennium 2003, 19-21 May 2003, Canary Islands, Spain. Ι.Papaefstathiou, “Titan II : An IPComp Processor for 10Gbit/sec networks”, IEEE Computer Society Annual Symposium On VLSI Feb 20-21, 2003, Tampa, Florida. I. Papaefstathiou, C. Sotiriou, "Read, Use, Simulate, Experiment and Build : An Integrated Approach for Teaching Computer Architecture" , 8th Workshop on Computer Architecture Education (WCAE 2002), 29th International Symposium on Computer Architecture (ISCA 2002), Anchorage, Alaska, USA, 26 May 2002. I. Papaefstathiou, "An Ultra High-Speed Compressor for Packet Networks" , 8th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2001), Valetta, Malta, 2-6 September 2001. I. Papaefstathiou, "A complete framework for on-line Compression of ATM streams", IEEE/IEE International Conference on Telecommunications 2000 (ICT 2000), Acapulco, Mexico, 22-25 May 2000. I. Papaefstathiou, "Measurement based Connection Admission Control algorithm for ATM networks that use low level compression", 7th International Conference on Intelligence in Services and Networks, IS&N 2000, Lecture Notes in Computer Science n. 1774, pp. 138-146,Athens, Greece, 25-28 February 2000. I.Papaefstathiou, Brown A., Simer J., Sobel D., Sutaria J., Wang S. Y., Blackwell T., Smith M., Yang W, "An IRAM-Based Architecture for a Single-Chip ATM Switch", 6th IEEE International Conference on Electronics, Circuits and Systems (ICECS '99), Paphos, Cyprus, 5-8 September 1999. I. Papaefstathiou, "Compressing ATM streams on-line", 1999 IEEE Data Compression Conference (DCC'99), Utah, USA, 29-31 March 1999. I. Papaefstathiou, "Accelerating ATM : On-line compression of ATM streams", 18th IEEE International Performance, Computing, and Communications Conference (IPCCC'99), Phoenix, Arizona, USA, 10-12 February 1999. Brown, A., D. Chian, N. Mehta, I. Papaefstathiou, J. Simer, T. Blackwell, M. Smith, W. Yang, "Using MML to Simulate Multiple Dual-Ported SRAMs: Parallel Routing Lookups in an ATM Switch Controller". 1997 Workshop on Mixing Logic and DRAM, International Symposium of Computer Architecture (ISCA '97), Denver, Colorado, USA, 1 June 1997. Technical Reports I. Papaefstathiou, " Increasing packet network bandwidth through low level compression", Ph.D. Thesis, Computer Lab, University of Cambridge, January 2001. Brown A., I. Papaefstathiou, J. Simer, D. Sobel, J. Sutaria, S. Wang, T. Blackwell, M. Smith, W. Yang, "An IRAM-Based Architecture for a Single-Chip ATM Switch", Technical Report TR-07-97, Center for Research in Computing Technology, Harvard University, 1997. I. Papaefstathiou "A behavioral model of ATLAS I (ATm multi-LAne Switch I) and the supporting modules for providing the input ATM traffic to ATLAS I and to the behavioral model(BeSwitch), and for checking the outputs of the two switches", Senior Thesis, Advisor : Prof. M. Katevenis, Computer Science Department, University of Crete, Iraklio, Crete, Greece, July 1996.