Dionisios Pnevmatikatos

Citation List

September 1999

This list contains citations to papers published before 1996 from selected only conference and publications.


Article: Todd M. Austin, Dionisios N. Pnevmatikatos, and Gurindar S. Sohi, "Streamlining Data Cache Access with Fast Address Calculation," Proceedings of the 22nd Annual International Symposium on Computer Architecture (ISCA-22), pp. 369-380, June 1995, IEEE/ACM.

Citations: 7 + 2 self-references by other co-author(s).
 

Article: Dionisios N. Pnevmatikatos and Gurindar S. Sohi, "Guarded Execution and Branch Prediction in Dynamic ILP Processors," Proceedings of the 21st Annual International Symposium on Computer Architecture (ISCA-21), pp. 120-129, April 1994, IEEE/ACM.

Citations: 13 + 2 self-references by other co-author(s).
 

Article: Dionisios N. Pnevmatikatos, Manoj Franklin, and Gurindar S. Sohi, "Control Flow Prediction for Dynamic ILP Processors," Proceedings of the 26th Annual International Symposium on Microarchitecture (MICRO-26), pp. 153-163, December 1993, IEEE/ACM.

Citations: 1 + 1 self-reference by other co-author(s).
 

Article: Jeffrey D. Gee, Mark D. Hill, Dionisios N. Pnevmatikatos, and Alan J. Smith, "Cache Performance of the SPEC92 Benchmark Suite," IEEE Micro, vol. 13, n. 4, pp. 17-27, August 1993.

Citations: 32 + 1 self-reference by other co-author(s).


 
 

Citations in
Without
self-references
Self-references by other co-authors
Books:
2
–
Journal articles:
13
–
Conference articles:
35
6
Newsletters:
3
–
Total Citations:
53
6
Total Citations: 53 + 6 self-reference by other co-author(s).

Detailed Citation List

Shaded citations indicate self-references by co-authors of the referenced paper


Article: Todd M. Austin, Dionisios N. Pnevmatikatos, and Gurindar S. Sohi, "Streamlining Data Cache Access with Fast Address Calculation," Proceedings of the 22nd Annual International Symposium on Computer Architecture (ISCA-22), pp. 369-380, June 1995, IEEE/ACM.

Citations: 9
 

Journal Citations:

  1. A Partitioned On-chip Virtual Cache for Fast Processors, D.W. Kim, J.W. Lee and S.K. Park, Journal of System Architectures, Vol. 43, no 8, 1997, pp. 519-531.
  2. Value Profiling and Optimization, Brad Calder Peter Feller, Journal of Instruction-Level Parallelism, Vol. 1, No. 1, 1999 pp. 1-6.
Selected Conference Citations:
  1. Zero-Cycle Loads: Microarchitecture Support for Reducing Load Latency, T. Austin, G. Sohi, Proceedings of the 28th Annual International Symposium on Microarchitecture (ISCA-28), November 1995, IEEE/ACM.
  2. Exceeding the Dataflow Limit via Value Prediction, M. Lipasti, J. Shen, Proceedings of the 29th Annual International Symposium on Microarchitecture (MICRO-29), December 1996, IEEE/ACM.
  3. Predictive Sequential Associative Cache, B. Calder, D. Drunwald, J. Emer, Proceedings of the Second International Symposium on High-Performance Computer Architecture (HPCA-2), February 1997, IEEE.
  4. Streamlining Inter-operation Memory Communication via Data Dependence Prediction, A. Moshovos, G. Sohi, Proceedings of the 30th Annual International Symposium on Microarchitecture (MICRO-30), December 1997, IEEE/ACM.
  5. The Design and Performance of a Conflict-avoiding Cache, N. Topham, A. Gonzalez, J. Gonzalez, Proceedings of the 30th Annual International Symposium on Microarchitecture (MICRO-30), December 1997, IEEE/ACM.
  6. Low Load Latency through Sum-Addressed Memory (SAM), W. Lynch, G. Lauterbach, J. Chamdani, Proceedings of the 25th Annual International Symposium on Computer Architecture (ISCA-25), June 27-July 1 1998, IEEE/ACM.
  7. Load Execution Latency Reduction, Bryan Black, Brian Mueller, Stephanie Postal, Ryan Rakvic, Noppanunt Utamaphethai, and John Paul Shen, Proceedings of the 12th International Conference on Supercomputing (ICS), July 12-17 1998, ACM.

Article: Dionisios N. Pnevmatikatos and Gurindar S. Sohi, "Guarded Execution and Branch Prediction in Dynamic ILP Processors," Proceedings of the 21st Annual International Symposium on Computer Architecture (ISCA-21), pp. 120-129, April 1994, IEEE/ACM.

Citations: 15
 

Journal Citations:

  1. Enhancing Multiple-Path Speculative Execution with Predicate Window Shifting, J.Y. Tsai and P.-C. Yew, Journal of System Architecture - Special Issue on Microprocessor Architecture, North Holland, Vol. 45, Nos. 12/13, 1999.
Selected Conference Citations:
  1. The Anatomy of the Register File in a Multiscalar Processor, S. Breach, T. Vijaykumar, G. Sohi, Proceedings of the 27th Annual International Symposium on Microarchitecture (MICRO-27), November 1994, IEEE/ACM.
  2. The Effects of Predicated Execution on Branch Prediction, G. Tyson, Proceedings of the 27th Annual International Symposium on Microarchitecture (MICRO-27), November 1994, IEEE/ACM.
  3. Characterizing the Impact of Predicated Execution on Branch Prediction, S. Mahlke, R. Hank, R. Bringmann, J. Gyllenhaal, D. Gallagher, W.M. Hwu, Proceedings of the 27th Annual International Symposium on Microarchitecture (MICRO-27), November 1994, IEEE/ACM.
  4. A Comparison of Full and Partial Predicated Execution Support for ILP Processors, S. Mahlke, R. Hank, J. McCormick, D. August, W.M. Hwu, Proceedings of the 22nd Annual International Symposium on Computer Architecture (ISCA-22), May 1995, IEEE/ACM.
  5. Multiscalar Processors, G. Sohi, S. Breach, T. Vijaykumar, Proceedings of the 22nd Annual International Symposium on Computer Architecture (ISCA-22), May 1995, IEEE/ACM.
  6. Compiler Technology for Future Microprocessors, Wen-mei W. Hwu, Richard E. Hank, David M. Gallagher, Scott A. Mahlke, Daniel M. Lavery, Grant E. Haab, John C. Gyllenhaal, and David I. August, Proceedings of the IEEE, 1995, IEEE.
  7. Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures, E. Hao, P-Y. Chang, M. Evers, Y. Patt, Proceedings of the 29th Annual International Symposium on Microarchitecture (MICRO-29), December 2-4, 1996, IEEE/ACM.
  8. Architectural Support for Compiler-Synthesized Dynamic Branch Prediction Strategies: Rationale and Initial Results, David I. August, Daniel A. Connors, John C. Gyllenhaal, and Wen-mei W. Hwu, Proceedings of the Third International Symposium on High-Performance Computer Architecture (HPCA-3), February 1997, IEEE/ACM.
  9. The Bi-Mode Branch Predictor, C-C. Lee, I-C. Chen, T. Mudge, Proceedings of the 30th Annual International Symposium on Microarchitecture (MICRO-30), December 1997, IEEE/ACM.
  10. A Framework for Balancing Control Flow and Predication, David I. August, Wen-mei W. Hwu, and Scott A. Mahlke, Proceedings of the 30th International Symposium on Microarchitecture (MICRO-30), December 1-3, 1997, IEEE/ACM.
  11. Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture, D. August, D. Connors, S. Mahlke, J. Sias, K. Crizier, B. Cheng, P. Eaton, Q. Olaniran, W. Hwu, Proceedings of the 25th Annual International Symposium on Computer Architecture (ISCA-25), June 27-July 1 1998, IEEE/ACM.
  12. Dynamic Hammock Prediction for Non-Predicated Instruction Set Architectures, A. Klauser, T. Austin, D. Grunwald, and B. Calder, Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), 1998, IEEE.
  13. Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture (1998) David I. August, Daniel A. Connors, Scott A. Mahlke, John W. Sias, Kevin M. Crozier, Ben-Chung, Cheng Patrick, R. Eaton, Qudus B. Olaniran, and Wen-mei W. Hwu, Proceedings of the 25th International Symposium on Computer Architecture (ISCA-25), June 27-July 1, 1998, pp. 227-237, IEEE/ACM.
Newsletter Citations:
  1. Demystifying EPIC and IA-64, Peter Song, Microprocessor Report, January 26, 1998, pp 21-27.


Article: Dionisios N. Pnevmatikatos, Manoj Franklin, and Gurindar S. Sohi, "Control Flow Prediction for Dynamic ILP Processors," Proceedings of the 26th Annual International Symposium on Microarchitecture (MICRO-26), pp. 153-163, December 1993, IEEE/ACM.

Citations: 2
 

  1. Control Flow Prediction with Tree-Like Subgraphs for Superscalar Processors, S. Dutta, M. Franklin, Proceedings of the 28th Annual International Symposium on Microarchitecture (MICRO-28), November 1995, IEEE/ACM.
  2. Multiple-Block Ahead Branch Predictors, Andre Seznec, Stephan Jourdan, Pascal Sainrat and Pierre Michaud, Proceedings of the 7th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VII), Boston, MA, October 1996.


Article: Jeffrey D. Gee, Mark D. Hill, Dionisios N. Pnevmatikatos, and Alan J. Smith, "Cache Performance of the SPEC92 Benchmark Suite," IEEE Micro, vol. 13, n. 4, pp. 17-27, August 1993.

Citations: 33
 

Book Citations:

  1. John Hennessy, David Patterson, Computer Architecture, a Quantitative Approach, Second Edition, Morgan Kaufman, 1996.
  2. Trace-Driven Memory Simulation: a Survey, R. Uhlig and T. Mudge, White Book on Performance Evaluation. Springer-Verlag, to appear.
Journal Citations:
  1. Design Considerations for the PowerPC-601 Microprocessor, Vaden MT, Merkel LJ, Moore CR, Potter TM, Reese RJ, IBM Journal of Research and Development, Vol. 38, No. 5, pp. 605-620, September 1994.
  2. Quantifying Behavioral-Differences between C and C++ Programs, Calder B, Grunwald D, Zorn B, Journal of Programming Languages, Vol 2, No. 4, pp. 313-351, December 1994.
  3. Quantifying Behavioral Differences Between C and C++ Programs, Brad Calder, Dirk Grunwald and Benjamin Zorn, Journal of Programming Languages, Vol. 2, No. 4, pp. 313-351, 1994.
  4. Measuring Cache and TLB Performance and their Effect on Benchmark Runtimes, Saavedra RH, Smith AJ, IEEE Transactions on Computers, Vol. 44, No. 10, pp. 1223-1235, October 1995.
  5. The Architecture of a High-Performance Mass Store With GMR Memory Cells, Pohm AV, Daughton JM, Brown J, Beech R, IEEE Transactions On Magnetics, Vol. 31 no 6, pp. 3200-3202, Part 1, November 1995.
  6. SH3 - High Code Density, Low-Power, Hasegawa A, Kawasakai I, Yamada K, Yoshioka S, Kawasaki S, Biswas P, IEEE Micro, Vol. 15, No. 6, pp. 11-19, December 1995.
  7. Active Memory: A New Abstraction For Memory System Simulation, Alvin R. Lebeck and David A. Wood, ACM Transactions on Modeling and Computer Simulation, Vol. 7, No. 1, pp. 42-77, January 1997.
  8. Design of a 32 b Monolithic Microprocessor Based On GaAs HMESFEt Technology, Tien CKV, Lewis K, Greub HJ, Tsen T, McDonald JF, IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol. 5, No. 2, pp. 238-243, June 1997.
  9. Trace-driven Memory Simulation: a Survey, Richard A. Uhlig and Trevor N. Mudge, ACM Computing Surveys, Vol. 29, No. 2, pp. 128-170, June 1997.
  10. Minimizing Area Cost of On-Chip Cache Memories by Caching Address Tags, H. Wang, T. Sun, Q. Yang, IEEE Transactions on Computers, Vol. 46. No. 11, November 1997.
Selected Conference Citations:
  1. Characterization of Alpha AXP Performance Using TP and APEC Workloads Z. Cvetanivic, D. Bhandarkar, Proceedings of the 21st Annual International Symposium on Computer Architecture (ISCA-21), April 1994, IEEE/ACM.
  2. The Effectiveness of Caches for Vector Processors, J. Gee, A. J. Smith, Proceedings of the 1994 International Conference on Supercomputing (ICS), July 1994, ACM.
  3. Trap-Driven Simulation with Tapeworm II, R. Uhlig, D. Nagle, T. Mudge, and S. Sechrest, Proceedings 6th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VI), pp. 132-144, October 1994, ACM/IEEE.
  4. Memory Behavior of an X11 Window System, J. Bradley Chen, Proceedings of the USENIX Winter 1994 Technical Conference, 1994, USENIX.
  5. Improving Performance by Cache Driven Memory Management, K. Westerholz, S. Honal, J. Plankl, C. Hafer, Proceedings of the First International Symposium on High-Performance Computer Architecture (HPCA-1), January 1995, ACM.
  6. Instruction Fetching: Coping with Code Bloat, R. Uhlig, D. Nagle, T. Mudge, S. Sechrest, J. Emer, Proceedings of the 22nd Annual International Symposium on Computer Architecture (ISCA-22), May 1995, IEEE/ACM.
  7. CAT - Caching Address Tags A Technique for Reducing Area Cost of On-Chip Caches, H. Wang, T. Sun, Q. Yang, Proceedings of the 22nd Annual International Symposium on Computer Architecture (ISCA-22), May 1995, IEEE/ACM.
  8. Active Memory: A New Abstraction for Memory-System Simulation, Alvin R. Lebeck and David A. Wood, Proceedings of the 1995 ACM SIGMETRICS Conference, May 1995, ACM.
  9. Cache Performance of Fast-Allocating Programs, Marcelo J. R. Goncalves and Andrew W. Appel, Proceedings of the Seventh International Conference on Functional Programming and Computer Architecture, pp. 293-305, ACM Press, June 1995, ACM.
  10. Cache Miss Heuristics and Preloading Techniques for General-Purpose Programs, T. Ozawa, Y. Kimura, S. Nishizaki, Proceedings of the 28th Annual International Symposium on Microarchitecture (MICRO-28), November 1995, IEEE/ACM.
  11. The Role of Adaptivity in Two-Level Adaptive Branch Prediction, S. Sechrest, C-C. Lee, T. Myudge, Proceedings of the 28th Annual International Symposium on Microarchitecture (MICRO-28), November 1995, IEEE/ACM.
  12. Correlation and Aliasing in Dynamic Branch Predictors, S. Sechrest, C-C. Lee, T. Mudge, Proceedings of the 23rd Annual International Symposium on Computer Architecture (ISCA-23), May 1996, IEEE/ACM.
  13. Don't use the page number but a pointer to it, A. Seznec, Proceedings of the 23rd Annual International Symposium on Computer Architecture (ISCA-23), May 1996, IEEE/ACM.
  14. The Difference-bit Cache, T. Juan, T. Lang, J. Navarro, Proceedings of the 23rd Annual International Symposium on Computer Architecture (ISCA-23), May 1996, IEEE/ACM.
  15. Increasing Cache Port Efficiency for Dynamic Superscalar Microprocessors, K. Wilson, K. Olukotlun, M. Rosenblum, Proceedings of the 23rd Annual International Symposium on Computer Architecture (ISCA-23), May 1996, IEEE/ACM.
  16. A Quantitative Analysis of Loop Nest Locality, Kathryn S. McKinley and Olivier Temam, Proceedings of the 7th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VII), October 1996, IEEE/ACM.
  17. Performance Analysis Using the MIPS R10000 Performance Counters, M. Zagha, B. Larson, S. Turner, M. Itzkowitz, The International Conference of High Performance Computing and Communications (Supercomputing Conference), November 17-22 1996, IEEE/ACM.
  18. Designing High Bandwidth On-Chip Caches, K. Wilson, K. Olukotlun, Proceedings of the 24th Annual International Symposium on Computer Architecture (ISCA-24), May 1997, IEEE/ACM.
  19. A Comparison of Software Code Reordering and Victim Buffers, Iris Bahar, Brad Calder and Dirk Grunwald, Third Workshop on Interaction between Compilers and Computer Architectures, October 1998.
Newsletter Citations:
  1. Improving Cache Performance With Balanced Tag And Data Paths, Peir JK, Hsu WW, Young H, Ong S, ACM Sigplan Notices, 31: (9), pp. 268-278, September 1996, ACM.
  2. A Quantitative Analysis of Loop Nest Locality, McKinley KS, Temam O, ACM Sigplan Notices, 31: (9), pp. 94-104, September 1996, ACM.