Vassilis Papaefstathiou is a Research Assistant in the Computer Architecture and VLSI Systems Laboratory at the Institute of Computer Science, FORTH and a Ph.D. Candicate in the Computer Science Department (CSD) at the University of Crete(UoC).

His research interests include: Computer Architecture, Parallel and High-Performance Computing, Packet Switch Architecture, High Speed Interconnects, Network Processing Architectures, Storage Systems and Embedded Systems.

More information about his current research activities can be found here.