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Outline

  • Introduction to the operation of an Internet Router

    • Control plane

      • Routing protocols
      • Routing table
      • Management interfaces

    • Datapath

      • Longest Prefix Match (LPM)
      • Classless Interdomain Routing (CIDR)
      • Header processing
      • Packet buffering

  • The NetFPGA Router

    • Hardware

      • Gigabit Ethernet interfaces
      • Field Programmable Gate Array (FPGA) Logic
      • Random Access Memory (RAM)

    • Software

      • Kernel-space driver
      • User-space applications
      • PCI host interface
    • System configuration

  • Demonstration Topology

    • Hardware

      • Network of ten routers
      • Ethernet switch
      • Video server
      • High Definition (HD) video client

    • Software

      • PW-OSPF
      • Routing tables
      • Dynamic re-routing

  • Integrated Circuit Design

    • Technologies

      • Look-Up Tables (LUTs)
      • Configurable Logic Blocks (CLBs)
      • Field Programmable Gate Arrays (FPGAs)

    • Verilog Hardware Description Langauge (HDL)

      • Registers, integers, arrays
      • Multiplexers
      • Synchronous storage elements
      • Finite State Machines (FSMs)

    • Hardware Debug

      • Waveform monitor
      • In-circuit logic emulation

  • NetFPGA System Components

    • Synthesis of tutorial router

    • Java-based Graphical User Interface (GUI)

      • Configuration
      • Statistics

    • Router architecture

      • Pipeline
      • Queues

  • Buffer Size Experiment

    • Experiment with TCP/IP flows

      • Rule-of-thumb for the buffer size
      • Round-trip propation delay
      • Capacity of bottlneck link
      • Number of active flows
    • Lower delay with smaller queues

  • Enhanced Router

    • Additional hardware

      • Event capture module
      • Rate limiter
      • Delay module

    • Experiments

      • Netperf
      • HD video transport

    • Life of packet through the system

      • Description of blocks
      • Waveforms from logic analyzer
  • Module Development and Testing
    • Running ModelSim with the NetFPGA TestBench
      • Compile, simulate, view waveforms
      • Example: Simply Encryption on a packet payload
      • Scrambling the payload with XOR using a key from a register
    • Regression testing to verify hardware functionality
      • Synthesize and run the hardware
      • Verify value: 0xFFFFFFFF (would invert every bit of every byte of payload)
      • Verify value: 0xFF00FF00 (would invert every other byte of payload)
      • Verify value: 0x55555555 (would invert every other bit of payload)
    • Slides: Will be available here.