Computer Architecture and VLSI Systems (CARV) Laboratory

ICS - CARV: R & D activities


ICS > CARV > R & D activities


	Research and Development The main research interests are included in the bellow two categories Packet Switch Architecture Operating Systems and HPCN R&D Projects Per-Flow Queueing Weighted-Round-Robin Scheduling Wormhole IP over ATM ATLAS I: 10 Gb/s Single-Chip ATM Switch with Backpressure Pipelined Memory Resource Discovery Cache Performance WWW Performance Network Memory Scheduling and Load Balancing Distributed Shared Memory Telegraphos: Networks of Workstations Other Research & Development Projects Demos Pipelined Memory Palantir

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Last revision date: 7 August, 2002 by web-team@ics.forth.gr
Last Content revision date: Dec. 1998 (major), 2001 (minor) by M. Katevenis URL: http://www.ics.forth.gr/carv/r-d-activities.html

Research and Development