Technical & Research Reports

Miscalleneous

• Klonatos, Y. (2011). Design and Evaluation of Solid-State Drive (SSD) Caches to Improve Storage I/O Performance. Σχεδιασμός και Αξιολόγηση Κρυφών μνημών με Solid-State Drives (SSD)για τη βελτίωση της απόδοσης της Ε/Ε αποθήκευσης. 

ICS-FORTH Technical Reports

• Tzenakis, G., Papatriantafyllou, A., Zakkak, F., Vandierendonck, H., Pratikakis , P., & Nikolopoulos, D. (2012). BDDT: Block-level Dynamic Dependence Analysis for Deterministic Task-Based Parallelism. 2012 TR426_Block-level_Dynamic_Dependence_Analysis_for_Deterministic_Task-Based_Parallelism.pdf
• Pratikakis , P., Chinis, G, Athanasopoulos, E., & Ioannidis, S. (2012). Practical Information Flow for Legacy Web Applications. 2012.TR428_Practical-Information_Flow_for_Legacy_Web_Applications.pdf
• Lyberis, S., & Kalokairinos, G. (2012). The 512-core Formic Hardware Prototype : Architecture Manual & Programmer's Model. 2012.TR430_The_512-core_Formic_Hardware_Prototype.pdf
• Passas, G. (2012). VLSI Micro-Architectures for High-Radix Crossbars. 2012.TR427_VLSI_Micro-Architectures_High-Radix_Crossbars.pdf
• Tsaliagos, D. (2011). Design and Implementation of a Directory based Cache Coherence Protocol. 2011.TR418_Directory_based_Cache_Coherence_Protocol.pdf
• Kavadias, S.G. (2010). Direct Communication and Synchronization Mechanisms in Chip Multiprocessors. 2010.TR411_Direct_Communication_Synchr_Mechanisms_Chip_Multiprocessors.pdf
• Nikiforos, G. (2010). FPGA implementation of a cache controller with configurable scratchpad space. 2010.TR402_FPGA_Cache_Controller.pdf
• Mihelogiannakis, G. (2007). Approaching Ideal NoC Latency with Pre-Configured Routes. 2007.TR391_Approaching_Ideal_NoC_Latency.pdf
• Papamichael, M. (2007). Network Interface Architecture and Prototyping for Chip and Cluster Multiprocessors. 2007.TR392_Network_Interface_Architecture_Chip_Cluster_Multiprocessors.pdf
• Chrysos, N.I. (2007). Request-Grant Scheduling for Congestion Elimination in Multistage Networks. 2007.TR388_Congestion_Elimination_Multistage_Networks.pdf
• Apostolopoulos, G. (2006). Building Extensible and Robust Networking Systems using Virtual Machines. 2006.TR384_Extensible_Robust_Networking_Systems.pdf
• Vlachos, E. (2006). Design and Implementation of a Coherent Memory Sub-System for Shared Memory Multiprocessors. 2006.TR382_Coherent_Memory_Sub-System_Multiprocessors.pdf
• Kalokairinos, G., Papaefstathiou, V., Ioannou, A., Simos, D.G., Papamichail, M., Mihelogiannakis, G., Marazakis, M., Pnevmatikatos, D., & Katevenis, M.G.H. (2006). Design and Implementation of a Multi-Gigabit NIC and a Scalable Buffered Crossbar Switch. 2006.TR376_Design_Multi-Gigabit_NIC.pdf
• Apostolopoulos, G., & Ciurea, I. (2006). Reducing the Forwarding State Requirements of Point-to-Multipoint Trees Using MPLS Multicast. 2006.TR367_Reducing_Requirements_Point-to-Multipoint_Trees.pdf
• Flouris, M.D., Lachaize, R., & Bilas, A. (2006). Shared & Flexible Block I/0 for Cluster-Based Storage. 2006.TR380_Shared_Flexible_Block_Cluster-Based_Storage.pdf
• Apostolopoulos, G. (2006). Using Multiple Topologies for IP-only Protection Against Network Failures: A Routing Performance Perspective. 2006.TR377_Routing_Performance_Perspective.pdf
• Apostolopoulos, G., & Chasapis, K. (2006). V-eM: A Cluster of Virtual Machines for Robust, Detailed, and High-Performance Network Emulation. 2006.TR371_V-eM_Cluster_of_Virtual_Machines.pdf
• Matthaiakis, P. (2005). Study of the inter and intra die variability of the SPARTAN 2E FPGA using dual rail circuits. 2005.TR361_Spartan_2E_FPGA_using_dual_rail_circuits.pdf
• Kounalakis, E. (2005). The Mythical IP Block: An Investigation of Contemporary IP Characteristics. 2005.TR366.Mythical_IP_Block.pdf
• Andrikos, N. (2004). Automated Flow for Digital Circuits De-synchronization. 2004.TR338_Automated_Flow_for_Digital_Circuits_De-synchronization.pdf
• Simos, D.G. (2004). Design of a 32x32 Variable-Packet-Size Buffered Crossbar Switch Chip. 2004.TR339_Variable_Packet-Size_Buffered_Crossbar_Switch_Chip.pdf
• Vlachos, E. (2004). Study of asynchronous controllers" circuits in de-synchronized systems. 2004.TR337_Asynchronous_Controllers"_Circuits.pdf
• Flouris, M.D., & Bilas, A. (2004). Violin: A Framework for Extensible Block-level Storage. 2004.TR344_Violin_Framework_Extensible_Block-level_Storage.pdf
• Kokkalis, N.P. (2003). A Switching Fabric Simulator Accelerator using a systolic array of FPGA"s. 2003.TR321.Switching_Fabric_Simulator_Accelerator_using.FPGAs.pdf
• Flouris, M.D., & Bilas, A. (2003). Clotho: Transparent Data Versioning at the Block I/O Level. 2003.TR326_Clotho_Transparent_Data_Versioning.pdf
• Chrysos, N.I. (2003). Design Issues of Variable-Packet-Size, Multiple-Priority Buffered Crossbars. 2003.TR325_Multiple-priority_Buffered_Crossbars.pdf
• Passas, G. (2003). Performance Evaluation of Variable Packet Size Buffered Crossbar Switches. 2003.TR328_Evaluation_Packet-Size_Buffered_Crossbar_Switches.pdf
• Passas, G. (2003). Performance Evaluation of Variable Packet Size Buffered Crossbar Switches. 2003.TR328_Evaluation_Packet-Size_Buffered_Crossbar_Switches.pdf
• Antonatos, S., Anagnostakis, K.G., Markatos, E.P., & Polychronakis, M. (2002). Benchmarking and Design of String Matching Intrusion Detection Systems. 2002.TR315.benchmarking_ids.ps.gz
• Sapountzis, G., & Katevenis, M.G.H. (2002). Benes Fabrics with Internal Backpressure: First Work-in-Progress Report. 2002.TR303.Benes_Fabrics_Internal_Backpressure.ps.gz
• Sapountzis, G. (2002). Benes Switching Fabrics with 0(N)-Complexity Internal Backpressure. 2002.TR316.Bennes_Switching_Fabrics_Complexity_Internal_Backpressure.pdf.gz
• Kapsalis, D. (2002). Design and implementation of a per-flow queue manager for an ATM switch using FPGA Technology. 2002.TR302.Design_per_flow_queue_manager_FPGA_Technology.ps.gz
• Sotiriou, Ch.P. (2002). Direct-Mapped Asynchronous Finite-State Machines in CMOS Technology. 2002.TR305.Direct-Mapped_Asynchronous_CMOS_Technology.pdf.gz
• Anagnostakis, K.G., Antonatos, S., Markatos, E.P., & Polychronakis, M. (2002). E2 XB: A Domain-Specific String Matching Algorithm for Intrusion Detection. 2002.TR311.Domain_String_Matching_Algorithm_Intrusion_Detection.ps.gz
• Markatos, E.P., Antonatos, S., Polychronakis, M., & Anagnostakis, K.G. (2002). Exclusion-based signature matching for intrusion detection. 2002.TR310.String_Matching_for_Intrusion_Detection.ps.gz
• Sotiriou, Ch.P. (2002). Implementing Asynchronous Circuits using a Conventional EDA Tool-Flow. 2002.TR306.Asynchronous_Circuits_using_Conventional_EDA_Tool-Flow.pdf.gz
• Portokalidis, G., Markatos, E.P., & Marazakis, M. (2002). Study and Bridging of Peer-to-Peer File Sharing Systems. 2002.TR312.Bridging_Peer-to-Peer_File_Sharing_Systems.pdf.gz
• Chrysos, N.I., & Katevenis, M.G.H. (2002). Weighted Max-Min Fair Scheduling for an Input-Buffered Crossbar Switch, with Small Internal Memory. 2002.TR309.Max_Min_Fair_Scheduling_Input_Buffered_Crossbar_Switch.ps.gz
• Markatos, E.P. (2001). Speeding up TCP / IP : Faster Processors are not Enough. 2001.TR297.SpeedingUp_TCP_IP_faster_processors.ps.gz
• Markatos, E.P. (2001). Tracing a large-scale Peer to Peer System: an hour in the life of Gnutella. 2001.TR298.Tracing_Peer_to_Peer_System.ps.gz
• Ioannou, A. (2000). An ASIC Core for Pipelined Heap Management to Support Scheduling in High Speed Networks. 2000.TR278.ASIC_Core_Pipelined_Heap_High_Speed_Networks.ps.gz
• Markatos, E.P., Pnevmatikatos, D., Flouris, M.D., & Katevenis, M.G.H. (2000). Web-Conscious Storage Management for Web Proxies. 2000.TR275.Web-Conscious_Storage_Management_Web-Proxies.ps.gz
• Katehakis, D.G., Chalkiadakis, G., Tsiknakis, M.N., & Orphanoudakis, S.C. (1999). A distributed, agent-based architecture for the acquisition, management, archiving and display of real-time monitoring data in the intensive care unit.. 1999.TR261.Intensive-Care_CORBA_SoftwareAgents_real-time-ICU-monitoring.ps.gz
• Dollas, A., Papadimitriou, K., Mathioudakis, C., Markatos, E.P., & Katevenis, M.G.H. (1999). Experimental ATM Network Interface Performance Evaluation. 1999.TR244.ATM_if_perf.ps.gz
• Mavroidis, I. (1999). Hardware Implementation of a Routine Filter to support Wormhole IP over ATM. 1999.TR258.RoutingFilterCore.ps.gz
• Sapountzis, G. (1999). Routing Table Organization and Management in the Wormhole IP Routing Filter. 1999.TR257.RTOrgMng.ps.gz
• Markatos, E.P. (1998). A Cash-based Approach to Caching Web Documents. 1998.TR230.cash_based_caching.ps.gz
• Katevenis, M.G.H., Serpanos, D.N., & Spyridakis, E. (1998). Credit-Flow-Controlled ATM for MP Interconnection: the ATLAS I Single-Chip ATM Switch. 1998.HPCA.atlas4mp.ps.gz
• Glykopoulos, G. (1998). Design and Implementation of a 1.2 Gbit/s ATM Cell Buffer using a Synchronous DRAM chip. 1998.TR221.ATM_Cell_Buffer_using_SDRAM.ps.gz
• Mavroidis, I. (1998). Heap Management in Hardware. 1998.TR222.Heap_Management_in_Hardware.ps.gz
• Kornaros, G., Pnevmatikatos, D., Vatsolaki, P., Kalokairinos, G., Xanthaki, Ch., Mavroidis, D., Serpanos, D.N., & Katevenis, M.G.H. (1998). Implementation of ATLAS I: a Single-Chip ATM Switch with Backpressure. 1998.HOTI.atlasIimpl.ps.gz
• Papathanasiou, A E., & Markatos, E.P. (1998). Lightweight Transactions on Networks of Workstations. 1998.ICDCS.ps.gz
• Ioannidis, S., Markatos, E.P., & Sevaslidou, J.E. (1998). On Using Network Memory to Improve the Performance of Transaction -Based Systems. 1998.PDTA.RVM_EXODUS.ps.gz
• Pnevmatikatos, D., Markatos, E.P., Magklis, G.I., & Ioannidis, S. (1998). On Using Network RAM as a non-volatile Buffer. 1998.TR227.NVRAM.ps.gz
• Flouris, M.D., & Markatos, E.P. (1998). The Network RamDisk : Using Remote Memory on Heterogeneous NOWs. 1998.TR226.nrd_TR.ps.gz
• Markatos, E.P., Katevenis, M.G.H., & Vatsolaki, P. (1998). The Remote Enqueue Operation on Networks of Workstations. 1998.CANPC98.REQ.ps.gz
• Katevenis, M.G.H., Vatsolaki, P., Serpanos, D.N., & Markatos, E.P. (1997). ATLAS I: A Single-chip ATM switch for NOWs. 1997.CANPC97.ATLAS.ps.gz
• Katevenis, M.G.H. (1997). Buffer Requirements of Credit-Based Flow Control when a Minimum Draining Rate is Guaranteed. 1997.HPCS97.drain_cr_buf.ps.gz
• Markatos, E.P., Katevenis, M.G.H., Kalokairinos, G., Magklis, G.I., Milolidakis, G., & Oikonomou, Th. (1997). Issues in the Design and Implementation of User-Level DMA. 1997.TR182.UDMA.ps.gz
• Papathanasiou, A E., & Markatos, E.P. (1997). Lightweight Transactions on Networks of Workstations. 1997.TR209.Lightweight_Transactions_on_NOWs.ps.gz
• Katevenis, M.G.H., Serpanos, D.N., & Markatos, E.P. (1997). Multi-Queue Management and Scheduling for Improved QoS in Communication Networks. 1997.EMMSEC.Muqpro.ps.gz
• Ioannidis, S., Markatos, E.P., & Sevaslidou, J.E. (1997). On using Network Memory to Improve the Performance of Transaction-Based Systems. 1997.TR190.Remote_memory_RVM.ps.gz
• Kornaros, G., Kozyrakis, Ch., Vatsolaki, P., & Katevenis, M.G.H. (1997). Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control. 1997.ARVLSI.Pipe_MultiQueue.ps.gz
• Artavanis, M. (1997). Simulation of the Shared Disks Architecture for Transaction Processing Systems. 1997.TR211.Simulation_SharedDisks_Archit_Transaction_Processing_Systems.ps.gz
• Katevenis, M.G.H., Serpanos, D.N., & Spyridakis, E. (1997). Switching Fabrics with Internal Backpressure using the ATLAS I Single-Chip ATM Switch. 1997.GLOBECOM.ATLAS_I_Fabrics.ps.gz
• Markatos, E.P., & Katevenis, M.G.H. (1997). User-Level DMA without Operating System Kernel Modification. 1997.HPCA97.user_level_dma.ps.gz
• Markatos, E.P. (1997). Visualizing Working Sets. 1997.TR192.Visualizing_working_sets.ps.gz
• Markatos, E.P., & Chronaki, C. (1996). A Top-10 Approach to Prefetching on the Web. 1996.TR173.Web_Prefetching.ps.gz
• Nikolaou, Ch., Markatos, E.P., Karavassili, M., & Saridakis, T. (1996). ArrayTracer: A Parallel Performance Analysis Tool. 1996.TR162.ArrayTracer_A_Parallel_Performance_Analysis_Tool.ps.gz
• Katevenis, M.G.H., Serpanos, D.N., & Vatsolaki, P. (1996). ATLAS I: A General-Purpose, Single-Chip ATM Switch with Credit-Based Flow Control. 1996.HOTI.ATLAS_I_ATMswitchChip.ps.gz
• Katevenis, M.G.H., & Vatsolaki, P. (1996). ATLAS I: A Single-Chip ATM Switch with HIC Links and Multi-Lane Back-Pressure. 1996.EMSYS96.ATLAS_I_ATMswitchHIC.ps.gz
• Spyridakis, E. (1996). Comparison of Credit Based ATM and Wormhole Under Bursty Traffic or With Hot Spots. 1996.TR170.ATM_vs_Wormhole_in_Greek.ps.gz
• Katevenis, M.G.H., Vatsolaki, P., & Chalkiadakis, V. (1996). Credit-Flow-Controlled ATM over HIC Links in the ASICCOM ''ATLAS I"" Single-Chip Switch. 1996.RTMagazine.ATLAS_I_ATMswitchChip.ps.gz
• Katevenis, M.G.H., Serpanos, D.N., & Spyridakis, E. (1996). Credit-Flow-Controlled ATM versus Wormhole Routing. 1996.TR171.ATM_vs_Wormhole.ps.gz
• Markatos, E.P., & Dramitinos, G. (1996). Implementation of a Reliable Remote Memory Pager. 1996.usenix.ps.gz
• Markatos, E.P. (1996). Issues in Reliable Network Memory Paging. 1996.MASCOTS96.Reliable_Network_Memory.ps.gz
• Markatos, E.P., & Katevenis, M.G.H. (1996). Telegraphos :High-Performance Networking for Parallel Processing on Workstation Clusters.. 1996.HPCA96.Telegraphos.ps.gz
• Kozyrakis, Ch. (1996). The Architecture, Operation, and Design of the Queue Management Block in the ATLAS I ATM Switch. 1996.TR172.QueueManagement.ps.gz
• Markatos, E.P. (1996). Using Remote Memory to avoid Disk Thrashing: A Simulation Study. 1996.MASCOTS96.Remote_memory_paging.ps.gz
• Efthymiou, A. (1995). Design, Implementation, and Testing of a 25 Gb/s Pipelined Memory Switch Buffer in Full-custom CMOS. 1995.TR143.Design_Implementation_25Gbs_PipelinedMem_Switch_Buffer.ps.gz
• Markatos, E.P., Dramitinos, G., & Papachristos, K. (1995). Implementation and Evaluation of a Remote Memory Pager. 1995.TR129.remote_memory_paging.ps.gz
• Labrinidis, A. (1995). Methods to cluster transactions into utilization classes with similar workload characteristics. 1995.TR135.Methods_cluster_transactions_similar_workload_characteristics.ps.gz
• Katevenis, M.G.H., Vatsolaki, P., & Efthymiou, A. (1995). Pipelined Memory Shared Buffer for VLSI Switches. 1995.SIGCOMM95.PipeMemoryShBuf.ps.gz
• Katevenis, M.G.H., Vatsolaki, P., Efthymiou, A., & Stratakis, M. (1995). VC-level Flow Control and Shared Buffering in the Telegraphos Switch. 1995.HOTI.VCflowCtrlTeleSwitch.ps.gz
• Xanthaki, Z. (1994). A Memory Controller for Access Interleaving over a single Rambus. 1994.TR124.RAMBUS_AccessInterleaving_MemoryController.ps.gz
• Chatzaki, M. (1994). A Translation Scheme Between Two Real-Time Formalisms. 1994.TR128.specification_automatic_verification_timed_automata.ps.gz
• Dimitriadis, G. (1994). An Arithmetic Entropy Codec VLSI chip for JPEG Image Compression. 1994.TR114.Arithmetic_Entropy_Codec_VLSI_chip_for_JPEG.ps.gz
• Katevenis, M.G.H. (1994). FORTH, ICS: Computer Architecture and VLSI Systems Group: A Profile. 1994.AVG_PROFILE.ps.Z
• Katevenis, M.G.H., Vatsolaki, P., & Efthymiou, A. (1994). Pipelined Memory Organization for High Performance Switching and Buffering. 1994.TR127.PipelinedMemory.ps.Z
• Katevenis, M.G.H. (1994). Telegraphos: High-Speed Communication Architecture for Parallel and Distributed Computer Systems. 1994.TR123.Telegraphos.ps.Z
• Markatos, E.P., & Chronaki, C. (1994). Using reference counters in Update Based Coherent Memory. 1994.PARLE94.Reference_Counters.ps.Z
• Markatos, E.P. (1993). How Architecture Evolution Influences the Scheduling Discipline used in Shared-Memory Multiprocessors. 1993.PARCO93.Architecture_infuence_on_Scheduling.ps.Z
• Markatos, E.P., & Leblanc, Th.J. (1993). Locality-Based Scheduling in Shared-Memory Multiprocessors. 1993.TR94.Locality_Based_Scheduling.ps.Z
• Markatos, E.P., & Chronaki, C. (1993). Trace-Driven Simulation of Data-Alignment and other Factors affecting Update and Invalidate Based Coherent Memory. 1993.TR93.DATA_ALIGNMENT_IN_VIRTUAL_SHARED_MEMORY.ps.Z
• Markatos, E.P., & LeBlanc, T.J. (1993). Using Processor Affinity in Loop Scheduling on Shared-Memory Multiprocessors. 1993.TPDS.Affinity_Loop_Scheduling.ps.Z
• Vatsolaki, P. (1992). Design of a High-Speed UART VLSI Library Cell. 1992.TR50.High_Speed_UART_VLSIlibCell.ps.Z
• Sidiropoulos, S. (1991). A General Purpose ATM Switch Chip : Architecture and Feasibility Study. 1991.TR025_General_Purpose_ATM_Switch_Chip.pdf
• Sidiropoulos, S. (1991). Fast Packet Switches for Asynchronous Transfer Mode. 1991.TR25.Fast_packet_switches.ps.Z
• Katevenis, M.G.H. (1987). Fast Switching and Fair Control of Congested Flow in Broad-Band Networks. 1987.TR001_Fast-Switching_Fair-Control_Broad-Band-Networks.pdf

M.S. Theses

• Chasapis, K. (2012). Bladefs: Design and Implementation of a kernel level file system for scalable storage servers. 
• Papatriantafyllou, A. (2012). Efficient and Accurate Block-Level Dependence Analysis For Task Dataflow Models. 
• Stamatakis, D. (2012). Scalability of Replicated Metadata Services in Distributed File Systems . 
• Zakkak, F. (2012). SCOOP: Language extensions and compiler optimizations for task-based programming models. 
• Klonatos, I. (2011).  Design and Evaluation of Solid-State Drive (SSD) Caches to Improve Storage I/O Performance. University of Crete Α. Μπίλας
• Tsaliagkos, D. (2011). Design and Implementation of a Directory based Cache Coherence Protocol. 
• Saloustros, G. (2011). Design and Implementation of a Scalable Storage System for Fully-Consistent Replicated Data Logging. 
• Kesapidis, I. (2011). Dynamic Dependence Analysis on Multi-core Processors. 
• Fountoulakis, M. (2010). DARC: Design and Evaluation of an I/O Controlller for data Protection. May 2010
• Alvanos, M. (2010). Design and Evaluation of a Task -based Paraller H.264 Video Encoder for the Cell Processor. July 2010
• Koukos, K. (2010). Locality management in task-based parallel programming models. August 2010
• Zampetakis, M. (2010). Runtime support for programming explicit communication chip multiprocessors. July 2010
• Sempepou, Z. (2010). Scalable storage support and fault-tolerance for data stream processing systems. July 2010
• Katsamali, M. (2010). Software implementation of MPI primitives in multicore FPGA. June 2010
• Makatos, A. (2010). ZBD: Using Transparent Compression at the Block Level to Increase Storage Space Efficiency. March 2010
• Nikiforos, G. (2009). FPGA implementation of a cache controller with configurable scratchpad space. April 2009
• Tzenakis, G. (2009). Tagged Procedure Calls (TPC): Efficient runtime support for task-based parallelism on the Cell Processor. November 2009
• Kasapaki, E. (2008). An EDA Tool for the Timing Analysis, Optimization and Timing Validation of Asynchronous Circuits. 2008
• Passas, S. (2008). Analysis and Optimization of Overheads in Communication Protocols Over High Speed Ethernet-based Cluster Interconnects. April 2008
• Mangas, E. (2008). Fine-grained Localization in Wireless Sensor Networks using Acoustic Sound Transmissions and High Precision Clock Synchronization. December 2008
• Aslanidis, I. (2008). Multi-valued logic synthesis. April 2008
• Pantelias, E. (2008). Αποσυγχρονισμός Βιομηχανικών Κυκλωμάτων. April 2008
• Michelogiannakis, G. (2007). Approaching Ideal NoC Latency with Pre-Configured Routes. September 2007
• Matthaiakis, P. (2007). Gated Dual-Rail - A Methodology for Reducing the Power Consumption of Monotonic Dual-Rail Circuits. December 2007
• Papamichail, M. (2007). Network Interface Architecture and Prototyping for Chip and Cluster Multiprocessors. September 2007
• Andrikos, N. (2006). A Fully-Automated Desynchronization Flow for Synchronous Circuits. April 2006
• Vlachos, E. (2006). Design and Implementation of a Coherent Memory Sub-System for Shared Memory Multiprocessors. April 2006
• Kotsis, G. (2006). Improving Scalability on Shared Memory Clusters. December 2006
• Passas, G. (2006). Packet Mode Scheduling in Buffered Crossbar Switches. April 2006
• Panagiotakis, G. (2006). Reducing Disk I/O Performance Sensitivity for Large Numbers of Sequential Streams. September 2006
• Giannakopoulos, I. (2005). CORMOS: A Communication-Oriented Runtime System for Wireless Sensor Networks. April 2005
• Papaefstathiou, V. (2005). Design and Implementation of Network Packet Classification Engines. April 2005
• Dokianaki, O. (2005). Evaluation of Asynchronous Interconnect Techniques for Digital SoC. April 2005
• Xynidis, D. (2005). Performance Analysis and Scaling of Networked Shared Block-Level Storage. December 2005
• Kounalakis, E. (2005). The Mythical IP Block: An Investigation of Contemporary IP Characteristics. December 2005
• Simos, D.G. (2004). Design of a 32x32 Variable Packet-Size Buffered Crossbar Switch Chip. November 2004
• Xynidis, K. (2004). Network Intrusion Prevention on Multilevel Processing Architectures. November 2004
• Sarmpanis, A. (2004). Ένα Πρωτόκολλο Εκμισθώσεων για την Ενημέρωση Δεδομένων Προσωρινών Μνημών peer-to-peer δικτύων. November 2004
• Charitakis, I. (2004). Εφαρμογές του Επεξεργαστή Δικτύων IXP 1200 σε Συστήματα Ανίχνευσης Εισβολέων για Δίκτυα. April 2004
• Papachristos, Ch. (2002).  Navigation Technologies over low bandwidth links for Thin Clients An introduction to the CC/PP protocol. December 2002
• Kapsalis, D. (2002). Design and Implementation of a per-Flow Queue Manager of an ATM Switch using FPGA Technology. March 2002
• Charteros, K. (2002). Fast Parallel Comparison Circuis for Scheduling. March 2002
• MeÃntanis, D. (2002). Hardware Conversion and Software Import to a Prototype Microprocessor Board. December 2002
• Kalyvianaki, E. (2002). Î§-PacketQ a network tragic visualization tool. A reial-time approach for multiple users. December 2002
• Lymperis, S. (2002). Implementation of a Motion Compensaation Subsystem for an MPEG-II Decoder. December 2002
• Chrysos, N. (2002). Weighted Max-Min Fair Scheduling, for a Crossbar, with Small Internal Memory. 2002
• Sapountzis, G. (2002). Πλέγματα Μεταγωγής BENES με Εσωτερικό Backpressure Πολυπλοκότητας O(N). December 2002
• Papadakis, G. (2001). Design and FPGA Implementation of an ABR traffic scheduler and utopia interfaces for an ATM network switch. November 2001
• Gialama, A. (2001). Distributed Video Server with Quality of Service. June 2001
• Asimakopoulou, X.A. (2001). Effective Resource Discovery on the World Wide Web. June 2001
• Danalis, A. (2001). Firewall development for the embedded network processor IXP1200. July 2001
• Lolas, Ch. (2001). Low Level Software Design and Implementation for High Performance Packet Switches. November 2001
• Ioannou, A. (2000). An ASIC Core for Pipelining Heap Management to Support Scheduling in High Speed Networks. November 2000
• Oikonomou, A. (2000). Architecture and Implementation of an Adaptation Bridge for ATM Networks. June 2000
• Flouris, M.D. (2000). Design & Implementation of Methods Enchancing the Performance of www Proxies. March 2000
• Nikologiannis, A. (2000). Efficient Per-Flow Queuing in DRAM at OC-192 Line Rate using Out-of-Order Execution Techniques. November 2000
• Sidiropoulos, A. (1999). Distributed Indexing and Searching Mechanisms. March 1999
• Chatzistamatiou, A. (1999). EasyAgent: a Masif Compliant Environment for Mobile Java Objects. March 1999
• Papathanasiou, A E. (1999). Effective Resource Discovery on the World Wide Web. June 1999
• Milolidakis, G. (1999). MemSpyer: A Performance Debugging Tool which simulates and visualizes memory hierarchy. March 1999
• Glykopoulos, G. (1998). Design and Ιmplementation of an 1.2 Gbit/s ATM Cell Buffer using a Synchronous DRAM chip. July 1998
• Karakonstantis, P. (1998). Efficient Memory Management for high-speed ATM networks. November 1998
• Kornaros, G. (1997).  Implementation of Pipelined Multi- Queue Management in the ATLAS I Switch in Full- Custom CMOS VLSI. June 1997
• Zarras, A. (1997). Array Tracer : Parallel Performance Analysis and Visualization. March 1997
• Gkanas, L. (1997). New Caching ways in the World Wide Web. 1997
• Terzis, S. (1997). Performance Monitoring in Digital Library Systems. November 1997
• Artavanis, M. (1997). Simulation of the Shared Discks Architecture for Transaction Processing Systems. November 1997
• Moraiti, M. (1997). Trace-driven Simulation of ATM and Wormhole networks. November 1997
• Anastasiadi, A. (1996).  A study of Microeconomic Algorithms for Load Balancing and Data Replication in Distributed Computer Systems. November 1996
• Spyridakis, E. (1996). Comparative Study of Credit Flow Controled ATM and Wormhole Networks Under Bursty Traffic and Witg Hot Spots. 1996
• Papachristos, K. (1996). Design and Implementation of the Telegraphos Operations for the Mach Operating System. March 1996
• Dramitinos, G. (1996). Reliable Paging to Remote Main Memory in a Workstation Cluster. 1996
• Ioannidis, S. (1996). Using the Remote Main Memory in a Workstation Cluster for Reliability and Performance in Transactional Based Systems. November 1996
• Sareidakis, T. (1995). Array Tracer: A Parallel Performance Analysis Tool. November 1995
• Efthymiou, A. (1995). Design of a 25 Gbits/sec Pipelined Menory for Shared Buffer Network Switches. November 1995
• Marazakis, M. (1995). Simulation and Transaction Processing Systems and A Study of Methods for Performance Goal Satisfaction. November 1995
• Lamprinidis, A. (1995). Μέθοδοι Ταξινόμησης Δοσοληψιών σε Ομάδες με Παρόμοια Χαρακτηριστικά Φόρτου Εργασίας. November 1995
• Karavasili, M. (1994). An Algorithm to Layout Directed Graphs. March 1994
• Dimitriadis, G. (1994). An Arithmetic Entropy Codec VLSI chip for JPEG compression. March 1994
• Xanthaki, Z. (1994). Ενας Ελεγκτής για Διαφύλλωση Προσπελάσεων σε ένα Απλό Rambus. March 1994
• Farsaris, I. (1993). Design and Implementation of undo-redo mechanism in Labyrinth System. May 1993
• Karydis, N. (1993). Βιβλιοθήκη Γεωμετρικών Κυττάρων και Μετασχηματισμών για τον Λαβύρινθο. April 1993
• Moschovos, A. (1992). Implementing non-numerical algorithms on a decoupled architecture supporting software pipelining. August 1992 (pdf in english) (pdf in greek)
• Kalogerakis, P. (1992). Ο Μηχανισμός Υπολογισμού Κυττάρων στο Λαβύρινθο. September 1992
• Sorilos, A. (1992). Οντοκεντρικός Σχεδιασμός Γραφικών στο Σύστημα Λαβύρινθος. September 1992
• Vatsolaki, P. (1992). Σχεδίαση Ενός Υψηλής Ταχύτητας UART Δομικού Στοιχείου για Βιβλιοθήκες Ολοκληρωμένων Κυκλωμάτων VLSI. 1992
• Georgis, Ch. (1992). Σχεδιασμός και Υλοποίηση του Γραφικού Τμήματος του Λαβυρίνθου. March 1992
• Sidiropoulos, S. (1991). A General Purpose ATM Switch Chip: Architecture and Feasibility Study. September 1991
• Tzartzanis, N. (1991). Αναδιάταξη Κώδικα σε Μνήμη Διπλού Πλάτους για Ελάττωση του Κόστους των Διακλαδώσεων. June 1991
• Chalkiadakis, V. (1990). Αρχική Σχεδίαση και Υλοποίηση του Ring 64: Δίκτυο Τοπολογίας Δακτυλίου για Πακέτα Δεδομένων και Φωνής με Ταχύτητα Μεγαλύτερη από 64 Mb/s. December 1990

Ph.D. Theses

• Kavadias, S.G. (2010). Direct Communication and Synchronization Mechanisms in Chip Multiprocessors. 
• Chrysos, N. (2007). Request- Grant Scheduling for Congestion Elimination in Multistage Networks. May 2007
• Marazakis, E. (2000). Service Composition and Service- level Agreements in Open Distributed Systems. December 2000

Other Technical Reports

• Faith, E., Fatourou, P., Kosmas, E., Milani, A., & Travers, C. (2012). Universal Constructions that Ensure Disjoint-Access Parallelism and Wait-Freedom.