Asynchronous Circuit and System Design Group

The following list of subjects taught at the Computer Science Department of the University of Crete relate to the interests of the Asynchronous Circuit and System Design Group:

Introduction to VLSI Systems [ CS422 ]

This is an introductory undergraduate course on the VLSI implementation of electronic circuits. The course explores the basics of CMOS transistor operation and CMOS gate design, the design of CMOS layouts of complex gates and subsystems, electrical effects on speed and area and reviews in detail several CMOS subsystems that are commonly used in contemporary ICs.

Computer Architecture [ CS425 ]

An undergraduate course on computer architecture concentrating on instruction-level parallelism and pipelining. The backbone of the course is the Hennesy-Patterson DLX architecture. The basic operation of a linear RISC pipeline is explored in depth, along with the concepts of spatial and temporal parallelism. Out-of-order architectures and approaches including scoreboarding and Tomasulo's algorithm are examined in detail.

EDA Tools for Digital VLSI Systems [ CS523 ]

This is a laboratory postgraduate course on ASIC/SoC design using industrial EDA/CAD tools. It is centered around a large ASIC/SoC student group project. The ASIC/SoC project is developed by each group of students from concept to mask layout implementation following all the individual steps of contemporary EDA flows.

System Timing and Synchronization [ CS590.20 ]

This is a postgraduate course which covers aspects of circuit timing. It begins from the basic principles of asynchronous designs including micropipelines, multi-rail encodings, studies the token model of circuits and presents approaches to asynchronous control circuit design based on STGs. It also studies the problem of multiple clock domain synchronization for various combinations of timing disciplines.

CAD Algorithms I [ CS590.24 ]

A postgraduate course on CAD algorithms for logic synthesis. It presents the key concepts behind boolean networks, the minimization of two-level circuits using exact and heuristic methods, extends into multiple level circuit representations including BDDs and ITEs and considers the multi-level synthesis and optimization methods and approaches for design-for-testability.

A number of presentations and teaching material on asynchronous design will appear on this webpage very soon...