Asynchronous Circuit and System Design Group

We are currently pursuing research and development into the following areas:

Asynchronous Design using Commercial EDA Tools (ASIC or FPGA)

The use of commercial EDA tools, ASIC or FPGA, for the implementation of asynchronous circuits and systems is indeed an R&D activity included in the ASPIDA project, but extends well beyond it. If asynchronous circuits are to be considered for broad adoption by industry we believe that the transition from synchronous to asynchronous must occur smoothly and by exploiting existing EDA technology and know-how instead of advocating a radical, instant change in design practices. The aim of this research is to focus on using commecial, industrial tools for asynchronous design and demonstrating that this is indeed possible. To achieve this goal it is often necessary to exploit specific features of these tools, including scripting, or develop help applications, which are incorporated in the design flow.

Asynchronous SoC Interconnects

System-on-Chip (SoC) interconnect has often been quoted as a very suitable application for asynchronous design. Being able to transmit data across IP blocks at non-multiples of clock cycles, without the need for clock domain synchronisation and the problem of clock skew is a very good solution to the problem of large-scale SOC design. Our research on asynchronous interconnects is concerned with identifying potential approaches for asynchronous SOC interconnects and both implement and evaluate these approaches using physical modelling techniques.

Asynchronous Design for Variability and High-performance

This research area aims to demonstrate that asynchronous circuits can indeed excibit better variability and higher-performance compared to their synchronous counterparts. Dual-rail or multi-rail logic implements asynchronous circuits with completion-detection. It has been shown by previous work that completion-detection alone is in most cases not sufficient for achieving better performance compared to that of a synchronous system. This work exploits techniques based on completion-detection that can indeed improve performance or enable better control of circuit variability.

Study of Bursting and Event Spacing Phenomena in Asynchronous Handshaking Structures

Asynchronous intercommunicating structures (e.g. rings) can excibit bursting or event spacing phenomena as has been shown in the literature. This research area aims at furthering the understanding of such phenomena, depending on the type of asynchronous circuits used, being able to control them and reason about them.