Asynchronous Circuit and System Design Group

Asynchronous Open-Source DLX Processor (ASPIDA)

ASPIDA is an EU-funded Demonstration project, which aims to demonstrate the industrial viability and IP Reuse potential of asynchronous parts by delivering a free, open-source, industrial-quality, asynchronous IP Processor Core, designed, tested and implemented using industrial EDA tools, which will support Open IP Reuse specifications, so it can be easily embedded into any Open IP System-On-a-Chip. The architecture executes the DLX instruction set, a well-known and well-supported generic RISC architecture designed for educational and research purposes. Inspired from the success of open-source software, this project aims to efficiently tackle the drawbacks of IP Reuse by promoting free, open-source hardware.

ASPIDA is a joint effort of FORTH-ICS, Politecnico di Torino, Manchester University and IHP Microelectronics.

The asynchronous DLX processor has been succesffully implemented both in ASIC and FPGA versions.

ASIC version	FPGA version

Read a comprehensive FAQ about ASPIDA here.

Interested in the desynchronized DLX? Find out how we did it by browsing our demo for the ASYNC 2004 conference!

The ASPIDA FAQ and files are also available as an Opencores project.